System Control Chip; Sc Chip Diagram - IBM z13s Technical Manual

2.3.5 System control chip

The SC chip uses the CMOS 14S0 22 nm SOI technology, with 15 layers of metal. It
measures 28.4 x 23.9 mm, has 7.1 billion transistors, and has 2.1 billion cells of eDRAM.
Each node of the CPC drawer has one SC chip. The L4 cache on each SC chip has 480 MB
of non-inclusive cache and a 224 MB non-data inclusive coherent (NIC) directory, which
results in 960 MB of on-inclusive L4 cache and 448 MB in a NIC directory that is shared per
CPC drawer.
Figure 2-15 shows a schematic representation of the SC chip.
L4 Cache L4 Cache
(120 MB + 56 MB NIC Directory) (120 MB + 56 MB NIC Directory)
Perv
Fabric
PLL
Data
Data
TOD
Fabric
L4 Controller
IOs
Bit-
Bit- IOs
Clk
Stack
Perv Stack
Perv
Repower
L4 Cache
L4 Cache
(120 MB + 56 MB NIC Directory)
(120 MB + 56 MB NIC Directory)
(480 MB + 224 MB NIC Directory)
Figure 2-15 SC chip diagram
Most of the SC chip space is taken by the L4 controller and the 480 MB L4 cache. The cache
consists of four 120 MB quadrants with 256 x 1.5 MB eDRAM macros per quadrant. The L4
cache is logically organized as 16 address-sliced banks, with 30-way set associative. The L4
cache controller is a single pipeline with multiple individual controllers, which is sufficient to
handle 125 simultaneous cache transactions per chip.
The L3 caches on PU chips communicate with the L4 caches through the attached SC chip
by using unidirectional buses. L3 is divided into two logical slices. Each slice is 32 MB, and
consists of two 16 MB banks. L3 is 16-way set associative. Each bank has 4 K sets, and the
cache line size is 256 bytes.
The bus/clock ratio (2:1) between the L4 cache and the PU is controlled by the storage
controller on the SC chip.
The SC chip also acts as an L4 cache cross-point switch for L4-to-L4 traffic to up to three
remote CPC drawers through three bidirectional data buses. The SMP cables and system
coherency manager use the L4 directory to filter snoop traffic from remote CPC drawers. This
process uses an enhanced synchronous fabric protocol for improved latency and cache
management. There are six clock domains, and the clock function is distributed between both
SC chips.
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Chapter 2. Central processor complex hardware components