Z13S Pu Core Logical Diagram - IBM z13s Technical Manual

Program results
The OoO execution does not change any program results. Execution can occur out of
(program) order, but all program dependencies are honored, ending up with the same results
of the in-order (program) execution.
This implementation requires special circuitry to make execution and memory accesses
display in order to the software. The logical diagram of a z13s core is shown in Figure 3-9.
Out-of-Order (OoO) addition
GCT
VBQ Issue Queue
VBU Fixed
Pt
GPR
1) on-the-fly OSC detection bubble-free
instruction expansion
2) banking for concurrent load/stores
prefetching enhancements
z13
Figure 3-9 s PU core logical diagram
Memory address generation and memory accesses can occur out of (program) order. This
capability can provide a greater use of the z13s superscalar core, and can improve system
performance.
Clump of instruction (up to 6)
Decode/Dispatch 1
Group of micro-ops (up to 6)
Rename
Issue Queue
Fixed Load/ Load/
Pt Store 2 Store
TLB
TLB0
L1 Dir
L2 Dir
Chapter 3. Central processor complex system design
InstQ
0cycE
Group of micro-ops (up to 6)
VBQ
micro-ops issue (up to 10)
Bin/Hex
Floating
2
Dec Flt
Pt
Pt
Fx Div
FPR
VBU
93