Reliability, Availability, And Serviceability; Ras In The Cpc Memory Subsystem - IBM z13s Technical Manual

memory is activated for actual use. For the exact terms and conditions, contact your IBM
representative.
Table 2-9 Feature codes for plan-ahead memory
Memory
Preplanned memory
Charged when physical memory is installed. Used for tracking
the quantity of physical increments of plan-ahead memory
capacity.
Preplanned memory activation
Charged when plan-ahead memory is enabled. Used for
tracking the quantity of increments of plan-ahead memory
being activated.
You install preplanned memory by ordering FC 1993 / 1996. The ordered amount of
plan-ahead memory is charged with a reduced price compared to the normal price for
memory. One FC 1993 is needed for each 8 GB physical increment, and one FC 1996 for
each 16 GB physical increment.
The activation of installed pre-planned memory is achieved by ordering FC 1903, which
causes the other portion of the previously contracted charge price to be invoiced. FC 1903
indicates 8 GB, and FC 1996 for 16 GB of LICCC increments of memory capacity.
Memory upgrades: Normal memory upgrades use up the plan-ahead memory first.

2.5 Reliability, availability, and serviceability

IBM z Systems continue to deliver enterprise class RAS with IBM z13s servers. The main
intent behind RAS is about preventing or tolerating (masking) outages and providing the
necessary instrumentation (in hardware, LIC/microcode, and software) to capture (collect) the
relevant failure information to help identify an issue without requiring a reproduction of the
event. These outages can be planned or unplanned. Planned and unplanned outages can
include the following situations (examples are not related to the RAS features of z Systems
servers):
A planned outage because of the addition of extra processor capacity
A planned outage because of the addition of extra I/O cards
An unplanned outage because of a failure of a power supply
An unplanned outage because of a memory failure
The z Systems hardware has decades of intense engineering behind it, which has resulted in
a robust and reliable platform. The hardware has many RAS features built into it.

2.5.1 RAS in the CPC memory subsystem

Patented error correction technology in the memory subsystem continues to provide the most
robust error correction from IBM to date. Two full DRAM failures per rank can be spared and a
third full DRAM failure can be corrected. DIMM level failures, including components such as
the memory controller application-specific integrated circuit (ASIC), the power regulators, the
clocks, and the system board can be corrected. Memory channel failures, such as signal
lines, control lines, and drivers/receivers on the SCM, can be corrected. Upstream and
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IBM z13s Technical Guide
z13s Feature Code /
Increment
FC 1993 / 8 GB
FC 1996 / 16 GB
FC 1903