Pu Chip Floorplan - IBM z13s Technical Manual

By design, each PU chip has eight cores. Core frequency is 4.3 GHz with a cycle time of
0.233 ns. When installed in a z13s server, the PU chips have either six or seven active cores.
This limit means that a Model N10 has 13 active cores, and the Model N20 has 26 active
cores. Model N10 has 10 customizable cores, whereas Model N20 has 20 customizable
cores. A schematic representation of the PU chip is shown in Figure 2-13.
Figure 2-13 PU Chip Floorplan
Each PU chip has 3.99 billion transistors. Each one of the eight cores has its own L1 cache
with 96 KB for instructions and 128 KB for data. Next to each core is its private L2 cache, with
2 MB for instructions and 2 MB for data.
Each PU chip has one L3 cache, with 64 MB. This 64 MB L3 cache is a store-in shared cache
across all cores in the PU chip. It has 192 x 512 KB eDRAM macros, dual address-sliced and
dual store pipe support, an integrated on-chip coherency manager, cache, and cross-bar
switch. The L3 directory filters queries from the local L4. Both L3 slices can deliver up to
16 GBps bandwidth to each core simultaneously. The L3 cache interconnects the eight cores,
GX++ I/O buses, PCIe I/O buses, and memory controllers (MCs) with SC chips.
The MC function controls access to memory. The GX++ I/O bus controls the interface to the
InfiniBand fanouts, while the PCIe bus controls the interface to PCIe fanouts. The chip
controls traffic between the cores, memory, I/O, and the L4 cache on the SC chips.
One coprocessor is dedicated for data compression and encryption functions for each core.
The compression unit is integrated with the CP Assist for Cryptographic Function (CPACF),
benefiting from combining (or sharing) the use of buffers and interfaces. The assist provides
high-performance hardware encrypting and decrypting support for clear key operations.
For more information, see 3.4.5, "Compression and cryptography accelerators on a chip" on
page 95.
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IBM z13s Technical Guide