IBM z13s Technical Manual page 142

memory distribution across the CPC drawers will be different, as will be the total amount of
available memory.
z13s CPC drawer memory information
On a z13s model N10 machine, the maximum amount of memory is limited to 984 GB of
customer addressable memory. If more memory is needed by the customer, a model upgrade
to Model N20 is mandatory. For availability and performance reasons, all available memory
slots in both nodes of the same CPC drawer are populated.
On a z13s Model N20 single CPC drawer machine, the maximum amount of memory is
limited to 2008 GB of customer addressable memory. If more memory is needed by the
customer, a model upgrade to Model N20 two CPC drawer model is mandatory (up to 4056
GB of customer usable memory). See Table 2-4 on page 53 for memory configuration options
and memory increments possible.
Note: Physical memory upgrade on a z13s server is disruptive.
Large page support
By default, page frames are allocated with a 4 KB size. z13s servers also support large page
sizes of 1 MB or 2 GB. The first z/OS release that supports 1 MB pages is z/OS V1R9. Linux
on z Systems support for 1 MB pages is available in SUSE Linux Enterprise Server (SLES)
10 SP2 and Red Hat Enterprise Linux (RHEL) 5.2.
The TLB exists to reduce the amount of time that is required to translate a virtual address to a
real address. This translation is done by dynamic address translation (DAT) when it must find
the correct page for the correct address space. Each TLB entry represents one page. Like
other buffers or caches, lines are discarded from the TLB on a least recently used (LRU)
basis. The worst-case translation time occurs during a TLB miss when both the segment table
(which is needed to find the page table) and the page table (which is needed to find the entry
for the particular page in question) are not in cache. This case involves two complete real
memory access delays plus the address translation delay. The duration of a processor cycle
is much shorter than the duration of a memory cycle, so a TLB miss is relatively costly.
It is preferable to have addresses in the TLB. With 4 K pages, holding all the addresses for
1 MB of storage takes 256 TLB lines. When you are using 1 MB pages, it takes only one TLB
line. Therefore, large page size users have a much smaller TLB footprint.
Large pages allow the TLB to better represent a large working set and suffer fewer TLB
misses by allowing a single TLB entry to cover more address translations.
Users of large pages are better represented in the TLB and can expect to see performance
improvements in both elapsed time and processor usage. These improvements are because
DAT and memory operations are part of processor busy time even though the processor waits
for memory operations to complete without processing anything else in the meantime.
To overcome the processor usage that is associated with creating a 1 MB page, a process
must run for some time. It must maintain frequent memory access to keep the pertinent
addresses in the TLB.
Short-running work does not overcome the processor usage. Short processes with small
working sets are expected to receive little or no improvement. Long-running work with high
memory-access frequency is the best candidate to benefit from large pages.
Long-running work with low memory-access frequency is less likely to maintain its entries in
the TLB. However, when it does run, a smaller number of address translations is required to
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IBM z13s Technical Guide