Omron CP1H-X40D Operation Manual page 257

Cpu unit sysmac cp series
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High-speed Counters
Note
I/O Allocation
Input Terminals
Input terminal
Word
Bit
CIO 0
00
01
02
03
04 to 07
08
09
10 and 11 Not used. (normal input)
CIO 1
00 to 11
The high-speed counter inputs are enabled when the Use high speed counter
0 Option is selected in the PLC Setup's Built-in Input Tab.
Output Terminals
Output terminal
Word
Bit
CIO 100
00
01
02 to 07
CIO 101
00 to 07
Auxiliary Area Addresses for High-speed Counter 0
PV storage words
Range Comparison
Condition Met Flag
Comparison In-
progress Flag
Overflow/Underflow
Flag
Count Direction Flag
Reset Bit
High-speed Counter
Gate Bit
Range Comparison Table
The range comparison table is stored in D10000 to D10039.
Start measurement by pushbutton switch (normal input).
Detect trailing edge of measured object (normal input).
Not used. (normal input)
Detect leading edge of measured object for high-speed
counter 0 phase-Z/reset input (see note). Bit status is reflected
in A531.00.
Not used. (normal input)
High-speed counter 0 phase-A input (See note.)
High-speed counter 0 phase-B input (See note.)
Not used. (normal input)
Normal input
PL1: Dimension pass output
Normal input
PL2: Dimension fail output
Normal input
Not used.
Normal input
Not used.
Function
Leftmost 4 digits
Rightmost 4 digits
Range 1 Comparison Condition Met Flag
ON when a comparison operation is being exe-
cuted for the high-speed counter.
ON when an overflow or underflow has occurred
in the high-speed counter's PV. (Used only when
the counting mode is set to Linear Mode.)
0: Decrementing
1: Incrementing
Used for the PV software reset.
When ON, the counter's PV will not be changed
even if pulse inputs are received for the counter.
Section 5-2
Usage
Usage
Address
A271
A270
A274.00
A274.08
A274.09
A274.10
A531.00
A531.08
223

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