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Altera MAX 10 User Manual

Altera MAX 10 User Manual

External memory interface
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MAX 10 External Memory Interface User
Last updated for Quartus Prime Design Suite: 16.0
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UG-M10EMI
101 Innovation Drive
2016.05.02
San Jose, CA 95134
www.altera.com
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Summary of Contents for Altera MAX 10

  • Page 1 MAX 10 External Memory Interface User Guide Last updated for Quartus Prime Design Suite: 16.0 UG-M10EMI 101 Innovation Drive Subscribe 2016.05.02 San Jose, CA 95134 Send Feedback www.altera.com...

  • Page 2: Table Of Contents

    LPPDDR2 Power Supply Variation Constraint................3-5 LPDDR2 Recommended Termination Schemes for MAX 10 Devices........3-6 Guidelines: MAX 10 DDR3, DDR2, and LPDDR2 External Memory Interface I/O Limitation..3-6 Guidelines: MAX 10 Board Design Requirement for DDR2, DDR3, and LPDDR2......3-8 Guidelines: Reading the MAX 10 Pin-Out Files..................3-8 MAX 10 External Memory Interface Implementation Guides......
  • Page 3 UniPHY Parameters—Controller Settings.................5-15 UniPHY Parameters—Diagnostics..................... 5-18 MAX 10 External Memory Interface User Guide Archives....... A-1 Additional Information for MAX 10 External Memory Interface User Guide ......................... B-1 Document Revision History for MAX 10 External Memory Interface User Guide......B-1 Altera Corporation...

  • Page 4: Max 10 External Memory Interface Overview

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 5: Max 10 External Memory Interface Support And Performance

    Planning Pin and FPGA Resources chapter, External Memory Interface Handbook • Provides the maximum number of interfaces supported by MAX 10 devices for each memory standards, pin counts for various external memory interface implementation examples, and informa‐ tion about the clock, address/command, data, data strobe, DM, and optional ECC signals.

  • Page 6: Max 10 External Memory Interface Architecture And Features

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 7: Max 10 Dq/Dqs Groups

    Table 2-1: Supported DQ/DQS Group Sizes in MAX 10 Devices and Packages This table lists the number of DQ/DQS groups supported on different MAX 10 devices and packages. Only the I/O banks on the right side of the devices support external memory interfaces.

  • Page 8: Max 10 External Memory Interfaces Maximum Width

    Related Information Planning Pin and FPGA Resources chapter, External Memory Interface Handbook Provides the maximum number of interfaces supported by MAX 10 devices for each memory standards, pin counts for various external memory interface implementation examples, and information about the clock, address/command, data, data strobe, DM, and optional ECC signals.
  • Page 9 UG-M10EMI MAX 10 External Memory Interfaces Maximum Width 2016.05.02 Table 2-2: Supported Maximum External Memory Interface Width in MAX 10 Device Packages Package Product Line F256 U324 F484 F672 10M16 — • x8 DDR2, • x8 DDR2, • x8 DDR2,...

  • Page 10: Max 10 Memory Controller

    • x16 LPDDR2 without DDR3/3L with • x16 LPDDR2 without ECC MAX 10 Memory Controller MAX 10 devices use the HPC II external memory controller. Table 2-3: Features of the MAX 10 Memory Controller Feature Description Half-Rate Operation The controller and user logic can run at half the memory clock rate.

  • Page 11: Max 10 External Memory Read Datapath

    MAX 10 External Memory Read Datapath In MAX 10 devices, instead of using DQS strobes, the memory interface solution uses internal read capture clock to capture data directly in the double data rate I/O (DDIO) registers in the I/O elements.

  • Page 12: Ddr Input Registers

    • Data is captured directly in the DDIO registers implemented in the I/O periphery. DDR Input Registers The DDR input capture registers in MAX 10 devices are implemented in the I/O periphery. Figure 2-3: External Memory Interface Read Datapath FPGA Core...

  • Page 13: Max 10 External Memory Write Datapath

    DQS, is not used during read operation. MAX 10 External Memory Write Datapath For all DDR applications supported by MAX 10 devices, the DQS strobe is sent to the external DRAM as center-aligned to the write DQ data. The clock that clocks DDIO registers of the DQ output is phase-shifted –90º from the clock that drives the DDIO registers of the DQS strobe.
  • Page 14 Transfer Register DDIO OUT dqs/dqs# GCLK AFI_CLK (HR) PHYCLK PHYCLK MEM_CLK (FR) clkin[0] clkout[0] PHYCLK DQ_WRITE_CLK (FR) clkin[1] clkout[1] PHYCLK READ_CAPTURE_CLK0 clkin[2] clkout[2] TRACKING_CLK clkin[3] clkout[3] MAX 10 External Memory Interface Architecture and Features Altera Corporation Send Feedback...

  • Page 15: Max 10 Address/Command Path

    MAX 10 Address/Command Path Altera's soft memory controller IP and PHY IP operate at half rate and issue address/command instructions at half-rate. MAX 10 External Memory Interface Architecture and Features Altera Corporation...

  • Page 16: Max 10 Phy Clock (Phyclk) Network

    In MAX 10 devices, only the top right PLL is routed to the PHYCLK tree. Therefore, the PHYCLK tree is available only for the I/O banks on the right side of the MAX 10 10M16, 10M25, 10M40, and 10M50 devices.

  • Page 17: Phase Detector For Vt Tracking

    PHYCLK READ_CAPTURE_CLK (FR) TRACKING_CLK (FR) In the MAX 10 external memory interface solution, the memory clocks are used to mimic the read and write paths. The memory clock pins loop back to the phase detector as a mimic clock. The phase detector provides any variation of the mimic clock to the sequencer.

  • Page 18: Phase-Locked Loop

    Provides more information about PLL location and availability in different MAX 10 packages. MAX 10 Low Power Feature The MAX 10 low power feature is automatically activated when the self refresh or low power down modes are activated. The low power feature sends the...

  • Page 19: Max 10 External Memory Interface Design Considerations

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 20 For DDR2/DDR3 interfaces, the address signals and the control or command signals are sent at a single data rate. You can use any of the user I/O pins on banks 5 & 6 of MAX 10 devices to generate the address and control or command signals to the external memory device.

  • Page 21: Ddr2/Ddr3 Recommended Termination Schemes For Max 10 Devices

    Note: Class I and Class II termination schemes in the following tables refer to drive strength and not physical termination. Table 3-1: Termination Recommendations for MAX 10 DDR2 Component Signal Type SSTL 18 I/O FPGA–End Discrete...

  • Page 22: Lpddr2 Design Considerations

    The MAX 10 devices support bidirectional data strobes. Connect the bidirectional DQ data signals to the same MAX 10 device DQ pins. The DQS pin is used only during write mode. In read mode, the MAX 10 PHY generates the read capture clock internally and ignores the DQS signal. However, you must still connect DQS signal to the MAX 10 DQS pin.

  • Page 23: Lppddr2 Power Supply Variation Constraint

    For LPDDR2 interfaces, the address signals and the control or command signals are sent at double data rate. You can use any of the user I/O pins on banks 5 & 6 of MAX 10 devices to generate the address and control or command signals to the external memory device.

  • Page 24: Lpddr2 Recommended Termination Schemes For Max 10 Devices

    LPDDR2 HSUL-12 34, 40, 48 34, 40, 48 Guidelines: MAX 10 DDR3, DDR2, and LPDDR2 External Memory Interface I/O Limitation While implementing certain external memory interface standards, the number of I/O pins available is limited. • While implementing DDR2—for 25 percent of the remaining I/O pins available in I/O banks 5 and 6, you can assign them only as input pins.
  • Page 25 UG-M10EMI Guidelines: MAX 10 DDR3, DDR2, and LPDDR2 External Memory Interface I/O... 2016.05.02 Package Device F256 U324 F484 F672 10M25 — — 10M40 — 10M50 MAX 10 External Memory Interface Design Considerations Altera Corporation Send Feedback...

  • Page 26: Guidelines: Max 10 Board Design Requirement For Ddr2, Ddr3, And Lpddr2

    Provides design guidelines related to signal integrity for MAX 10 devices. Guidelines: Reading the MAX 10 Pin-Out Files For the maximum number of DQ pins and the exact number per group for a particular MAX 10 device, refer to the relevant device pin-out files.

  • Page 27: Max 10 External Memory Interface Implementation Guides

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 28 Path Related Information Introduction to Altera IP Cores • Provides general information about all Altera IP cores, including parameterizing, generating, upgrading, and simulating IP. • Creating Version-Independent IP and Qsys Simulation Scripts Create simulation scripts that do not require manual updates for software or IP version upgrades.

  • Page 29: Lpddr2 External Memory Interface Implementation

    DM, and optional ECC signals. Supported LPDDR2 Topology For LPDDR2, the external memory interface IP for MAX 10 devices uses one capture clock and one tracking clock with one discrete device. Figure 4-3: Supported Topology for LPDDR2 Memory Interfaces This figure shows the supported LPDDR2 topology.

  • Page 30: Ddr2 And Ddr3 External Memory Interface Implementation

    DM, and optional ECC signals. MAX 10 Supported DDR2 or DDR3 Topology For DDR2 or DDR3/DDR3L, the external memory interface IP for MAX 10 devices uses two capture clocks with two discrete devices. MAX 10 External Memory Interface Implementation Guides...
  • Page 31 This figure shows the supported DDR2/DDR3 topology. One clock captures the lower 16 bit of data and the other clock captures the top 8 bit of data. The memory interface IP in MAX 10 devices generates DDR2 or DDR3/DDR3L IPs targeted for this configuration only.

  • Page 32: Uniphy Parameter Settings For Max 10

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 33 Rate on Avalon-MM interface The width of data bus on the Avalon-MM interface. The MAX 10 supports only Half rate, which results in a width of 4× the memory data width. Achieved local clock frequency The actual frequency the PLL generates to drive the local interface for the memory controller (AFI clock).

  • Page 34: Uniphy Parameters-Memory Parameters

    The number of chip-selects the IP core uses for the current device configuration. Specify the total number of chip-selects according to the number of memory device. Number of clocks The width of the clock bus on the memory interface. UniPHY IP Core References for MAX 10 Altera Corporation Send Feedback...
  • Page 35 Read burst type Specifies accesses within a given burst in sequential or interleaved order. Specify sequential ordering for use with the Altera memory controller. Specify interleaved ordering only for use with an interleaved-capable custom controller, when the Generate PHY only parameter is enabled on the PHY Settings tab.
  • Page 36 DDR2 and DDR3 SDRAM board layout, refer to the related information. To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results. UniPHY IP Core References for MAX 10 Altera Corporation Send Feedback...
  • Page 37 Read burst type Specifies accesses within a given burst in sequential or interleaved order. Specify sequential ordering for use with the Altera memory controller. Specify interleaved ordering only for use with an interleaved-capable custom controller, when the Generate PHY only parameter is enabled on the PHY Settings tab.

  • Page 38: Uniphy Parameters-Memory Timing

    • External Memory Interface Handbook Volume 1: Altera Memory Solution Overview and Design Flow Provides more information about using Altera devices for external memory interfaces including Altera memory solution and design flow. External Memory Interface Handbook Volume 2: Design Guidelines •...
  • Page 39 DQS signal received by the grade tQSH DDR3 memory. tDSH DDR2, DDR3, Memory speed DQS falling edge hold time from CK LPDDR2 grade (percentage of tCK). UniPHY IP Core References for MAX 10 Altera Corporation Send Feedback...

  • Page 40: Uniphy Parameters-Board Settings

    Calculate the value based on the memory clock clock frequency frequency. UniPHY Parameters—Board Settings There are three groups of options: Setup and Hold Derating, Channel Signal Integrity, and Board Skews. UniPHY IP Core References for MAX 10 Altera Corporation Send Feedback...
  • Page 41 Parameter Description Derating method Derating method. The default settings are based on Altera internal board simulation data. To obtain accurate timing analysis according to the condition of your board, Altera recommends that you perform board simulation and enter the slew rate in the Quartus Prime software to calculate the derated setup and hold time automatically or enter the derated setup and hold time directly.
  • Page 42 This section allows you to enter parameters to compensate for these variations. Note: Altera recommends that you use the Board Skew Parameter Tool to help you calculate the board skews. For more information, refer to the related information section.
  • Page 43 For multiple boards, the minimum skew between the CK signal and any DQS signal when arriving at the same DIMM over all DIMMs is expressed by the following equation, if you want to use the same design for several different boards: UniPHY IP Core References for MAX 10 Altera Corporation Send Feedback...
  • Page 44 (single or multiple chip-select, DIMM or component). For multiple boards, the largest skew between DQ and DM signals in a DQS group is expressed by the following equation: UniPHY IP Core References for MAX 10 Altera Corporation Send Feedback...
  • Page 45 For multiple boards, the largest skew between the address and command signals is expressed by the following equation, if you want to use the same design for several different boards: UniPHY IP Core References for MAX 10 Altera Corporation Send Feedback...

  • Page 46: Uniphy Parameters-Controller Settings

    Provides more information about derating method and measuring eye reduction. Board Skew Parameter Tool • UniPHY Parameters—Controller Settings There are four groups of options: Avalon Interface, Low Power Mode, Efficiency, and Configuration, Status and Error Handling. UniPHY IP Core References for MAX 10 Altera Corporation Send Feedback...
  • Page 47 Specifies the number of idle cycles after which the controller powers down the memory in the auto-power down cycles parameter. UniPHY IP Core References for MAX 10 Altera Corporation Send Feedback...
  • Page 48 Starvation limit for each Specifies the number of commands that can be served before a waiting command command is served. The valid range is from 1 to 63. UniPHY IP Core References for MAX 10 Altera Corporation Send Feedback...

  • Page 49: Uniphy Parameters-Diagnostics

    Enable Error Detection and Enables ECC for single-bit error correction and double-bit error Correction Logic detection. MAX 10 devices supports ECC only for 16 bits + 8 bits ECC memory configuration. Enable Auto Error Correction Allows the controller to perform auto correction when a single-bit error is detected by the ECC logic.

  • Page 50: Max 10 External Memory Interface User Guide Archives

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 51: Additional Information For Max 10 External Memory Interface User Guide

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 52 UG-M10EMI Document Revision History for MAX 10 External Memory Interface User... 2016.05.02 Date Version Changes May 2015 2015.05.04 • Updated the footnote in the topic about external memoy interface support and performance to specify that the default maximum frequency for LPDDR2 is 167 MHz.
  • Page 53 UG-M10EMI Document Revision History for MAX 10 External Memory Interface User... 2016.05.02 Date Version Changes September 2014 2014.09.22 Initial release. Additional Information for MAX 10 External Memory Interface User Guide Altera Corporation Send Feedback...

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