Altera MAX 10 User Manual
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Altera MAX 10 User Manual

Altera MAX 10 User Manual

User flash memory
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MAX 10 User Flash Memory User Guide
Last updated for Quartus Prime Design Suite: 16.0
UG-M10UFM
101 Innovation Drive
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2016.05.02
San Jose, CA 95134
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www.altera.com

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  • Page 1 MAX 10 User Flash Memory User Guide Last updated for Quartus Prime Design Suite: 16.0 UG-M10UFM 101 Innovation Drive Subscribe 2016.05.02 San Jose, CA 95134 Send Feedback www.altera.com...

  • Page 2: Table Of Contents

    Altera On-Chip Flash IP Core References............5-1 Altera On-Chip Flash Parameters......................5-1 Altera On-Chip Flash Signals........................5-2 Altera On-Chip Flash Registers......................... 5-4 MAX 10 User Flash Memory User Guide Archive..........A-1 Document Revision History for MAX 10 User Flash Memory User Guide..B-1 Altera Corporation...

  • Page 3: Max 10 User Flash Memory Overview

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 4: Max 10 Ufm Architecture And Features

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 5: Ufm Memory Organization Map

    UFM Block Diagrams This figure shows the top level view of the Altera On-Chip Flash IP core block diagram. The Altera On- Chip Flash IP core supports both parallel and serial interfaces for MAX 10 FPGAs. MAX 10 UFM Architecture and Features...
  • Page 6 These figures show the detailed overview of the Avalon-MM interface during read and program (write) operation. Figure 2-2: Altera On-Chip Flash IP Core Avalon-MM Slave Read and Program (Write) Operation in Parallel Mode This figure shows the standard interface for MAX 10 devices in parallel mode.
  • Page 7 UG-M10UFM UFM Block Diagrams 2016.05.02 Figure 2-3: Altera On-Chip Flash IP Core Avalon-MM Slave Read and Program (Write) Operation in Serial Mode This figure shows the standard interface for MAX 10 devices in serial mode. altera_onchip_flash clock clock reset_n reset_n...

  • Page 8: Ufm Operating Modes

    • Page erase • Sector write protection You can choose one of the following access modes in the Altera On-Chip Flash parameter editor to read and control the operations. • Read and program mode—this mode allows both data and control slave interface. This mode is applicable for both UFM and CFM sectors.
  • Page 9 • Hidden • Hidden Read Mode Incrementing burst read only • Incrementing burst read • Wrapping burst read Program (Write) Operation Single 32-bit parallel Single 32-bit serial program program operation operation MAX 10 UFM Architecture and Features Altera Corporation Send Feedback...

  • Page 10: Max 10 Ufm Design Considerations

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 11: Guideline: Ufm Content Initialization

    You can initialize the UFM content using either one of the following ways: • Set the initial memory content through the Altera On-Chip Flash IP core. • Set the initial memory content through the Convert Programming File tool in the Quartus Prime software when you convert .sof...

  • Page 12: Max 10 Ufm Implementation Guides

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 13: Ufm Write Control Register

    The flash IP core then sends address (control register) and (register value) to control the 0×01 writedata slave interface. UFM Program (Write) Operation The UFM offers a single 32-bit program (write) operation. MAX 10 UFM Implementation Guides Altera Corporation Send Feedback...
  • Page 14 The figure below shows the write data timing diagram in parallel mode. clock address addr write burstcount writedata data waitrequest UFM Programming Write UFM Reset Max 305 µs Typical 102 µs address Min 250 ns Min 34 µs to UFM MAX 10 UFM Implementation Guides Altera Corporation Send Feedback...

  • Page 15: Ufm Sector Erase Operation

    Note: Check the status register after each erase to make sure the erase operation is successful (erase successful). UFM Page Erase Operation The page erase operation allows the UFM to erase by pages. MAX 10 UFM Implementation Guides Altera Corporation Send Feedback...

  • Page 16: Ufm Read Operation

    1'b0 flash if you try to read from an illegal address or protected sector. The following figures show the timing diagrams for the read operations for the different MAX 10 devices in parallel and serial modes. MAX 10 UFM Implementation Guides...
  • Page 17 Figure 4-6: Read Operation for 10M40 and 10M50 Devices in Parallel Mode clock read write address addr burstcount waitrequest writedata readdatavalid readdata data0 MAX 10 UFM Implementation Guides Altera Corporation Send Feedback...

  • Page 18: Ufm Burst Read Operation

    UG-M10UFM UFM Burst Read Operation 2016.05.02 Figure 4-7: Read Operation for MAX 10 Devices in Serial Mode clock read write address addr burstcount waitrequest writedata readdatavalid readdata 31 30 29 28 27 26 5 4 3 2 1 0 UFM Burst Read Operation The burst read operation is a streaming 32-bit read operation.
  • Page 19 Figure 4-9: Incrementing Burst Read Operation for 10M16 and 10M25 Devices in Parallel Mode clock read write address addr addr burstcount waitrequest writedata readdatavalid readdata data1 data2 data3 data4 data5 data6 data7 data8 MAX 10 UFM Implementation Guides Altera Corporation Send Feedback...
  • Page 20 Figure 4-11: Unaligned Address Incrementing Burst Read Operation for 10M50 Devices in Parallel Mode clock read write addr address burstcount waitrequest writedata readdatavalid readdata data0 data1 data2 data3 data4 data5 data6 MAX 10 UFM Implementation Guides Altera Corporation Send Feedback...
  • Page 21 UG-M10UFM 4-10 UFM Data Wrapping Burst Read 2016.05.02 Figure 4-12: Incrementing Burst Read Operation for MAX 10 Devices in Serial Mode clock read write address addr burstcount waitrequest writedata readdatavalid readdata 63 62 61 60 59 58 31 30 29 28 27 26 UFM Data Wrapping Burst Read The UFM supports data wrapping when it receives an unaligned address.
  • Page 22 Figure 4-14: Wrapping Burst Read Operation for 10M16 and 10M25 Devices clock read write address addr0 addr1 burstcount waitrequest writedata readdatavalid readdata data0 data1 data2 data3 data4 data5 data6 data7 MAX 10 UFM Implementation Guides Altera Corporation Send Feedback...

  • Page 23: Flash Initialization Files

    Standard Altera memory initializa‐ For flash initialization in actual hardware. .mif tion file—uses word addressing. 32-bit data width file—uses word For flash initialization in simulation model. .dat addressing. MAX 10 UFM Implementation Guides Altera Corporation Send Feedback...

  • Page 24: Altera On-Chip Flash Ip Core References

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 25: Altera On-Chip Flash Signals

    This option is only available if you turn on Enable non-default initialization file. Assign your own simulation simulation filename. Altera On-Chip Flash Signals The following table lists the signals for the Altera On-Chip Flash IP core. Altera On-Chip Flash IP Core References Altera Corporation Send Feedback...
  • Page 26 32 • Serial mode: 1 Output The IP core asserts this bus to pause the master avmm_data_ when the IP core is busy during read or write waitrequest operations. Altera On-Chip Flash IP Core References Altera Corporation Send Feedback...

  • Page 27: Altera On-Chip Flash Registers

    10M04, and 10M08 1–2 10M16, 10M25, 1–4 10M40 and 10M50 Altera On-Chip Flash Registers The following table lists the address mapping and registers for the Altera On-Chip Flash IP core. Table 5-3: Altera On-Chip Flash Control Address Mapping Register Address Access Description Status Register 0×00...
  • Page 28 (CFM0 — protection bit) 31–10 dummy — All of these bits are set to 1. (padding) Table 5-5: Altera On-Chip Flash Control Register Bit Offset Field Default Value Description 19–0 pe (page erase All 1's Sets the page erase address to initiate a page address) erase operation.
  • Page 29 Disable write protected protection) 1'b0 mode wp (CFM1 write Enable write protected protection) 1'b1 mode wp (CFM0 write protection) 31–28 dummy — All of these bits are set to 1. (padding) Altera On-Chip Flash IP Core References Altera Corporation Send Feedback...

  • Page 30: Max 10 User Flash Memory User Guide Archive

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 31: Document Revision History For Max 10 User Flash Memory User Guide

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 32 UG-M10UFM Document Revision History for MAX 10 User Flash Memory User Guide 2016.05.02 Date Version Changes December 2014.12.15 • Added support for serial interface. 2014 • Added maximum operating frequency of 7.25 MHz for serial interface. • Updated the UFM block diagram to include serial interface.

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