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Altera MAX 10 User Manual

Altera MAX 10 User Manual

High-speed lvds i/o
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MAX 10 High-Speed LVDS I/O User Guide
101 Innovation Drive
UG-M10LVDS
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2016.10.31
San Jose, CA 95134
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  • Page 1 MAX 10 High-Speed LVDS I/O User Guide 101 Innovation Drive UG-M10LVDS Subscribe 2016.10.31 San Jose, CA 95134 Send Feedback www.altera.com...

  • Page 2: Table Of Contents

    Altera Soft LVDS Implementation Overview...................1-2 MAX 10 High-Speed LVDS Architecture and Features........2-1 MAX 10 LVDS Channels Support ......................2-1 MAX 10 LVDS SERDES I/O Standards Support..................2-7 MAX 10 High-Speed LVDS Circuitry.....................2-10 MAX 10 High-Speed LVDS I/O Location....................2-11 Differential I/O Pins in Low Speed Region.................... 2-14 MAX 10 LVDS Transmitter Design..............3-1...
  • Page 3 Altera Soft LVDS IP Core References..............7-1 Altera Soft LVDS Parameter Settings ....................... 7-1 Altera Soft LVDS Interface Signals......................7-7 MAX 10 High-Speed LVDS I/O User Guide Archives........A-1 Document Revision History for MAX 10 High-Speed LVDS I/O User Guide.. Altera Corporation...

  • Page 4: Max 10 High-Speed Lvds I/O Overview

    Provides a list of user guides for previous versions of the Altera Soft LVDS IP core. 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos ©...

  • Page 5: Altera Soft Lvds Implementation Overview

    Altera Soft LVDS Implementation Overview 2016.10.31 Altera Soft LVDS Implementation Overview You can implement LVDS applications in MAX 10 devices as transmitter-only, receiver-only, or a combination of transmitters and receivers. Figure 1-1: MAX 10 LVDS Implementation Overview Altera Soft LVDS...

  • Page 6: Max 10 High-Speed Lvds Architecture And Features

    This table lists the LVDS buffer support for I/O banks on each side of the devices. 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos ©...
  • Page 7 True LVDS Pairs Emulated LVDS Pairs Product Line Package Side Right Left Bottom Right M153 Left Bottom Right 10M02 U169 Left Bottom Right U324 Left Bottom Right E144 Left Bottom MAX 10 High-Speed LVDS Architecture and Features Altera Corporation Send Feedback...
  • Page 8 True LVDS Pairs Emulated LVDS Pairs Product Line Package Side Right M153 Left Bottom Right U169 Left Bottom Right 10M04 U324 Left Bottom Right F256 Left Bottom Right E144 Left Bottom MAX 10 High-Speed LVDS Architecture and Features Altera Corporation Send Feedback...
  • Page 9 Side Right Left Bottom Right M153 Left Bottom Right U169 Left Bottom Right 10M08 U324 Left Bottom Right F256 Left Bottom Right E144 Left Bottom Right F484 Left Bottom MAX 10 High-Speed LVDS Architecture and Features Altera Corporation Send Feedback...
  • Page 10 True LVDS Pairs Emulated LVDS Pairs Product Line Package Side Right U169 Left Bottom Right U324 Left Bottom Right 10M16 F256 Left Bottom Right E144 Left Bottom Right F484 Left Bottom MAX 10 High-Speed LVDS Architecture and Features Altera Corporation Send Feedback...
  • Page 11 F256 Left Bottom Right 10M25 E144 Left Bottom Right F484 Left Bottom Right F256 Left Bottom Right E144 Left Bottom 10M40 Right F484 Left Bottom Right F672 Left Bottom MAX 10 High-Speed LVDS Architecture and Features Altera Corporation Send Feedback...

  • Page 12: Max 10 Lvds Serdes I/O Standards Support

    MAX 10 LVDS SERDES I/O Standards Support The MAX 10 D and S device variants support different LVDS I/O standards. All I/O banks in MAX 10 devices support true LVDS input buffers and emulated LVDS output buffers. However, only the bottom I/O banks support true LVDS output buffers.
  • Page 13 UG-M10LVDS MAX 10 LVDS SERDES I/O Standards Support 2016.10.31 MAX 10 Device Support I/O Standard I/O Bank Notes Dual Single Supply Supply Device Device True LVDS Bottom • All I/O banks support banks true LVDS input buffers. only • Only the bottom I/O banks support true LVDS output buffers.
  • Page 14 UG-M10LVDS MAX 10 LVDS SERDES I/O Standards Support 2016.10.31 MAX 10 Device Support I/O Standard I/O Bank Notes Dual Single Supply Supply Device Device TMDS — — • Requires external termination but does not require V • Requires external level shifter to support 3.3 V...

  • Page 15: Max 10 High-Speed Lvds Circuitry

    4-4 MAX 10 High-Speed LVDS Circuitry The LVDS solution uses the I/O elements and registers in the MAX 10 devices. The Altera Soft LVDS IP core implements the serializer and deserializer as soft SERDES blocks in the core logic.

  • Page 16: Max 10 High-Speed Lvds I/O Location

    Provides more information about the PLL and the PLL output counters. MAX 10 High-Speed LVDS I/O Location The I/O banks in MAX 10 devices support true LVDS input and emulated LVDS output on all I/O banks. Only the bottom I/O banks support true LVDS output.
  • Page 17 This figure shows a top view of the silicon die. Each bank is labeled with the actual bank number. LVPECL support only in banks 2 and 6. LVDS Emulated LVDS RSDS Emulated RSDS Mini-LVDS Emulated Mini-LVDS PPDS Emulated PPDS BLVDS LVPECL TMDS Sub-LVDS SLVS HiSpi MAX 10 High-Speed LVDS Architecture and Features Altera Corporation Send Feedback...
  • Page 18 This figure shows a top view of the silicon die. Each bank is labeled with the actual bank number. LVPECL support only in banks 2 and 6. LVDS Emulated LVDS RSDS Emulated RSDS Mini-LVDS Emulated Mini-LVDS PPDS Emulated PPDS BLVDS LVPECL TMDS Sub-LVDS SLVS HiSpi MAX 10 High-Speed LVDS Architecture and Features Altera Corporation Send Feedback...

  • Page 19: Differential I/O Pins In Low Speed Region

    Differential I/O Pins in Low Speed Region Some of the differential I/O pins are located in the low speed region of the MAX 10 device. • For each user I/O pin (excluding configuration pin) that you place in the low speed region, the Quartus Prime software generates an informational warning message.
  • Page 20 2-15 Differential I/O Pins in Low Speed Region 2016.10.31 MAX 10 I/O Banks Locations, MAX 10 General Purpose I/O User Guide • Shows the locations of the high speed and low speed I/O banks. MAX 10 High-Speed LVDS Architecture and Features...

  • Page 21: Max 10 Lvds Transmitter Design

    The amount of pre-emphasis required depends on the attenuation of the high-frequency component along the transmission line. 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos ©...

  • Page 22: Programmable Differential Output Voltage

    LVDS output. Single-Ended Waveform Positive Channel (p) Negative Channel (n) Ground Differential Waveform (diff peak - peak) = 2 x V (single-ended) p - n = 0 V MAX 10 LVDS Transmitter Design Altera Corporation Send Feedback...

  • Page 23: Lvds Transmitter I/O Termination Schemes

    Allowed values 0 (low), 1 (medium), 2 (high). Default is 2. LVDS Transmitter I/O Termination Schemes For transmitter applications in MAX 10 devices, you must implement external termination for some I/O standards. Emulated LVDS External Termination The emulated LVDS transmitter requires a three-resistor external termination scheme.

  • Page 24: Slvs Transmitter External Termination

    Emulated RSDS, Emulated Mini-LVDS, and Emulated PPDS Transmitter External Termination The emulated RSDS, emulated mini-LVDS, or emulated PPDS transmitter requires a three-resistor external termination scheme. You can also use a single-resistor external termination for the emulated RSDS transmitter. MAX 10 LVDS Transmitter Design Altera Corporation Send Feedback...

  • Page 25: Lvds Transmitter Fpga Design Implementation

    MAX 10 devices use a soft SERDES architecture to support high-speed I/O interfaces. The Quartus Prime software creates the SERDES circuits in the core fabric by using the Altera Soft LVDS IP core. To improve the timing performance and support the SERDES, MAX 10 devices use the I/O registers and LE registers in the core fabric.

  • Page 26: Altera Soft Lvds Ip Core In Transmitter Mode

    Altera Soft LVDS IP Core in Transmitter Mode In the Quartus Prime software, you can design your high-speed transmitter interfaces using the Altera Soft LVDS IP core. This IP core uses the resources optimally in the MAX 10 devices to create the high-speed I/O interfaces.
  • Page 27 ALTPLL Signal Interface with Altera Soft LVDS Transmitter You can choose any of the PLL output clock ports to generate the LVDS interface clocks. If you use the ALTPLL IP core as the external PLL source of the Altera Soft LVDS transmitter, use the source-synchronous compensation mode.

  • Page 28: High-Speed I/O Timing Budget

    Altera Soft LVDS clock input ports. Initializing the Altera Soft LVDS IP Core The PLL locks to the reference clock before the Altera Soft LVDS IP core implements the SERDES blocks for data transfer. During device initialization the PLL starts to lock to the reference clock and becomes operational when it achieves lock during user mode.

  • Page 29: Guidelines: Lvds Transmitter Channels Placement

    Guidelines: LVDS Channels PLL Placement Each PLL in the MAX 10 device can drive only the LVDS channels in I/O banks on the same edge as the PLL. Table 3-4: Examples of Usable PLL to Drive I/O Banks in MAX 10 Devices...

  • Page 30: Guidelines: Enable Lvds Pre-Emphasis For E144 Package

    Provides step by step instructions about creating a design floorplan with LogicLock location assignments. Guidelines: Enable LVDS Pre-Emphasis for E144 Package For MAX 10 devices in the E144 package, Altera recommends that you enable LVDS pre-emphasis to achieve optimum signal integrity (SI) performance. If you do not enable pre-emphasis, undesirable SI condition may be induced in the device resulting in LVDS eye height sensitivity.

  • Page 31: Max 10 Lvds Receiver Design

    ABCDEFGH 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos © are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants...

  • Page 32: Data Realignment Block (Bit Slip)

    Description LVDS data stream, input to the Altera Soft LVDS channel. rx_in Clock used for receiver. fclk Enable signal for deserialization generated by the Altera Soft LVDS IP core. loaden Deserialized data. rx_out[9:0] Data Realignment Block (Bit Slip) Skew in the transmitted data and skew added by the transmision link cause channel-to-channel skew on the received serial data streams.

  • Page 33: Lvds, Mini-Lvds, And Rsds Receiver External Termination

    Figure 4-4: External Termination for SLVS Receiver 2.5 V = 50 Ω 100 Ω = 50 Ω SLVS peer SLVS on FPGA Sub-LVDS Receiver External Termination The Sub-LVDS receiver requires a single-resistor external termination scheme. MAX 10 LVDS Receiver Design Altera Corporation Send Feedback...

  • Page 34: Tmds Receiver External Termination

    50 Ω 50 Ω 0.1 µF = 50 Ω 0.1 µF = 50 Ω TMDS peer TMDS on FPGA HiSpi Receiver External Termination The HiSpi receiver requires a single-resistor external termination scheme. MAX 10 LVDS Receiver Design Altera Corporation Send Feedback...

  • Page 35: Lvpecl External Termination

    HiSpi peer HiSpi on FPGA LVPECL External Termination The MAX 10 devices support the LVPECL I/O standard on input clock pins only. • LVDS input buffers support LVPECL input operation. • LVPECL output operation is not supported. Use AC coupling if the LVPECL common-mode voltage of the output buffer does not match the LVPECL input common-mode voltage.

  • Page 36: Lvds Receiver Fpga Design Implementation

    Altera Soft LVDS IP Core in Receiver Mode In the Quartus Prime software, you can design your high-speed receiver interfaces using the Altera Soft LVDS IP core. This IP core uses the resources in the MAX 10 devices optimally to create the high-speed I/O interfaces.
  • Page 37 • The drawback of this method is that you can use the PLL only for the particular LVDS instance. Instantiate Altera Soft LVDS IP Core with External PLL You can set the Altera Soft LVDS IP core to build only the SERDES components but use an external PLL source.
  • Page 38 Determining External PLL Clock Parameters for Altera Soft LVDS Receiver 2016.10.31 If you use the ALTPLL IP core as the external PLL source of the Altera Soft LVDS receiver, use the source- synchronous compensation mode. Table 4-1: Example: Signal Interface Between ALTPLL and Altera Soft LVDS Receiver with Even...

  • Page 39: High-Speed I/O Timing Budget

    Altera Soft LVDS clock input ports. Initializing the Altera Soft LVDS IP Core The PLL locks to the reference clock before the Altera Soft LVDS IP core implements the SERDES blocks for data transfer. During device initialization the PLL starts to lock to the reference clock and becomes operational when it achieves lock during user mode.
  • Page 40 • A positive RSKM value, after deducting transmitter jitter, indicates that the LVDS receiver can sample the data properly. • A negative RSKM value, after deducting transmitter jitter, indicates that the LVDS receiver cannot sample the data properly. MAX 10 LVDS Receiver Design Altera Corporation Send Feedback...
  • Page 41 Related Information Guidelines: Control Channel-to-Channel Skew on page 6-1 RSKM Report for LVDS Receiver For LVDS receivers, the Quartus Prime software provides an RSKM report showing the SW, TUI, and RSKM values. MAX 10 LVDS Receiver Design Altera Corporation Send Feedback...
  • Page 42 • RSKM = (TUI – SW – RCCS) / 2 = (1000 ps – 300 ps – 300 ps) / 2 = 200 ps If the RSKM is greater than 0 ps after deducting transmitter jitter, the receiver will work correctly. MAX 10 LVDS Receiver Design Altera Corporation...

  • Page 43: Guidelines: Floating Lvds Input Pins

    Guidelines: LVDS Channels PLL Placement Each PLL in the MAX 10 device can drive only the LVDS channels in I/O banks on the same edge as the PLL. Table 4-3: Examples of Usable PLL to Drive I/O Banks in MAX 10 Devices...

  • Page 44: Guidelines: Lvds Receiver Logic Placement

    I/O interface. You can also use the Altera SignalTap II Logic Analyzer to perform system level verification to correlate the system against your design targets.
  • Page 45 UG-M10LVDS 4-15 Geometry-Based and Physics-Based I/O Rules 2016.10.31 For more information, refer to the related information. Related Information MAX 10 General Purpose I/O User Guide MAX 10 LVDS Receiver Design Altera Corporation Send Feedback...

  • Page 46: Max 10 Lvds Transmitter And Receiver Design

    DDIO Device 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos © are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants...

  • Page 47: Lvds Transmitter And Receiver Fpga Design Implementation

    MAX 10 devices use a soft SERDES architecture to support high-speed I/O interfaces. The Quartus Prime software creates the SERDES circuits in the core fabric by using the Altera Soft LVDS IP core. To improve the timing performance and support the SERDES, MAX 10 devices use the I/O registers and LE registers in the core fabric.

  • Page 48: Initializing The Altera Soft Lvds Ip Core

    MAX 10 device package that provides sufficient number of PLL clockouts for your design. Initializing the Altera Soft LVDS IP Core The PLL locks to the reference clock before the Altera Soft LVDS IP core implements the SERDES blocks for data transfer.

  • Page 49: Max 10 High-Speed Lvds Board Design Considerations

    Adjusting the trace length improves the channel-to-channel skew when interfacing with receivers. 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos © are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants...

  • Page 50: Guidelines: Determine Board Design Constraints

    • Jitter—jitter effects are derived from factors such as crosstalk. • Noise—on board resources with imperfect power supplies and reference planes may also cause noise. To ensure successful operation of the Altera Soft LVDS IP core receiver, do not exceed the timing budget. Related Information Board Design Guidelines Solution Center Provides resources related to board design for Altera devices.
  • Page 51 Related Information • Altera IBIS Models Provides IBIS models of Altera devices for download. • Altera HSPICE Models Provides SPICE models of Altera devices for download.

  • Page 52: Altera Soft Lvds Ip Core References

    Specifies the number of LVDS channels. channels 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos © are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants...
  • Page 53 Description Values SERDES factor — 1, 2, 4, 5, 6, 7, Specifies the number of bits per channel. 8, 9, 10 Table 7-2: Altera Soft LVDS Parameters - PLL Settings Parameter Condition Allowed Description Values Use external PLL Not applicable for x1 •...
  • Page 54 Specifies the phase shift parameter used by Data rate. inclock phase shift Functional mode = the PLL for the receiver. • Use external PLL = Table 7-3: Altera Soft LVDS Parameters - Receiver Settings Parameter Condition Allowed Description Values Enable bitslip General, Functional •...
  • Page 55 • Enable bitslip mode = On Use RAM buffer — • On If turned on, the Altera Soft LVDS IP core implements the output synchronization • Off buffer in the embedded memory blocks. This implementation option uses more logic than Use a multiplexer and synchroniza‐...
  • Page 56 Allowed Description Values Use logic element — • On If turned on, the Altera Soft LVDS IP core based RAM implements the output synchronization • Off buffer in the logic elements. This implementation option uses more logic than Use a multiplexer and synchroniza‐...
  • Page 57 Specifies which clock resource drives the 'tx_coreclock' Functional mode = selection output port. tx_coreclock • Global • Enable 'tx_ clock coreclock' output • Regional port = On clock • Dual- Regional clock Altera Soft LVDS IP Core References Altera Corporation Send Feedback...

  • Page 58: Altera Soft Lvds Interface Signals

    Altera Soft LVDS IP Core in Receiver Mode • on page 4-6 Altera Soft LVDS Interface Signals Depending on parameter settings you specify, different signals are available for the Altera Soft LVDS IP core. Table 7-5: Transmitter Interface Signals Signal Name...
  • Page 59 <J> is the deserialization factor and <n> is the number of channels. rx_in[0] drives data to rx_out[(<J>-1)..0] drives data to the next <J> number in[1] of bits on rx_out Altera Soft LVDS IP Core References Altera Corporation Send Feedback...
  • Page 60 Use the input signal rx_data_align_reset • You need to reset the PLL during device operation. • You need to re-establish the word alignment. Input <n> Controls byte alignment circuitry. rx_channel_data_align Altera Soft LVDS IP Core References Altera Corporation Send Feedback...
  • Page 61 <n> Asynchronous reset to the data realignment rx_cda_reset circuitry. This signal resets the data realign‐ ment block. The minimum pulse width requirement for this reset is one parallel clock cycle. Altera Soft LVDS IP Core References Altera Corporation Send Feedback...

  • Page 62: Max 10 High-Speed Lvds I/O User Guide Archives

    MAX 10 High-Speed LVDS I/O User Guide 14.1 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos © are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants...
  • Page 63 • Added the Power Supply Mode option. • Updated the allowed values of the SERDES factor parameter. 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos ©...
  • Page 64 • Removed the topics about generating IP cores and the files generated by the IP core, and added a link to Introduction to Altera IP Cores. • Removed the statement about getting TCCS value from the Quartus Prime compilation report.
  • Page 65 UG-M10LVDS Document Revision History for MAX 10 High-Speed LVDS I/O User Guide 2016.10.31 Date Version Changes May 2015 2015.05.04 • Removed the F672 package from the 10M25 device. • Updated the number of bottom true receiver channels for package M153 of the 10M02 device from 49 to 13.

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