Table of Contents
Advertisement
FX Series Programmable Controlers
5.9.5
CCD (FNC 84)
Mnemonic
CCD
FNC 84
(Check
Code)
16 BIT OPERATION
Points to note:
a) The SUM of the data stack is stored at destination D while the Parity for the data stack is
stored at D
b) During the Parity check an even result is indicated by the use of a 0 (zero) while an odd
parity is indicated by a 1 (one).
c) This instruction can be used with the 8 bit/ 16 bit mode flag M8161. The following results will
occur under these circumstances. See page 10-20 for more details about M8161.
Sourse (S)
FF
H
D100
L
FF
FF
H
D101
L
00
F0
H
D102
L
0F
Vertical
party
D1
SUM D0
It should be noted that when M8161 is OFF 'n' represents the number of consecutive bytes
checked by the CCD instruction. When M8161 is ON only the lower bytes of 'n' consecutive
words are used.
The 'SUM' is quite simply a summation of the total quantity of data in the data stack. The Parity
is checked vertically through the data stack as shown by the shaded areas.
Function
Checks the
KnX, KnY, KnM,
'vertical' parity of
KnS
a data stack
T, C, D
32 BIT OPERATION
.
+1
M8161=OFF
Bit patterm
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
3FC
Operands
S
D
KnY, KnM, KnS
T, C, D
Operation:
This instruction looks at a byte (8 bit) stack of data
from head address (S)for n bytes and checks the
vertical bit pattern for parity and sums the total
data stack. These two pieces of data are then
stored at the destination (D).
Sourse (S)
1
D100 L
1
D101 L
1
D102 L
0
D103 L
0
D104 L
1
D105 L
Vertical
0
party
D1
SUM D0
Applied Instructions 5
FX
FX
1S
1N
Program steps
n
K, H
CCD,
D
CCDP:
Note:
7 steps
n = 1 to 256
)
PULSE-P
M8161=ON
Bit patterm
FF
1
1
1
1
1
1
00
0
0
0
0
0
0
0F
0
0
0
0
1
1
F0
1
1
1
1
0
0
F0
1
1
1
1
0
0
0F
0
0
0
0
1
1
1
1
1
1
1
1
2FD
FX
FX
2N
2NC
1
1
0
0
1
1
0
0
0
0
1
1
1
1
5-123
Advertisement
Chapters
Table of Contents
