Target Board - Silicon Laboratories C8051F540DK User Manual

7. Target Board

The C8051F540 Development Kit includes a target board with a C8051F540 (Side A) and C8051F542 (Side B)
device pre-installed for evaluation and preliminary software development. Numerous input/output (I/O) connections
are provided to facilitate prototyping using the target board. Refer to Figure 3 for the locations of the various I/O
connectors. Figure 4 on page 9 shows the factory default shorting block positions. A summary of the signal names
and headers is provided in Table 9 on page 15.
P4 Header to choose between +5V from Debug Adapter (P2) or +5V from on-board regulator (U4)
J18 Connect V_HIGH node from TB1 LIN header to +5V regulator input for board power
P1 Power connector (accepts input from 7 to 15 VDC unregulated power adapter)
P5 USB connector (connects to PC for serial communication)
TB1 Shared LIN Connector for Side A and B MCUs for external nodes
J1-J3 Side A: Port 0 through Port 2 headers
J8 Side A: Connects +5V net to VIO and VREGIN of the MCU
J9, J10 Side A: External crystal enable connectors
J13 Side A: Connects decoupling capacitors C28 and C29 for MCU VREF (P0.0)
J15 Side A: Connects VIO to VIO_A_SRC which powers the R22 potentiometer, the RST_A
J16 Side A: Connects P1.3_A LED and P1.4_A Switch to MCU port pins
J17 Side A: Connects MCU to two separate transceivers (UART(U3), and LIN(T2))
J20 Side A: Connects R27 potentiometer to port pin 1.2
P2 Side A: DEBUG connector for Debug Adapter interface
TB3 Side A: Power supply terminal block
J4 Side B: Connects +5V net to VIO and VREGIN of the MCU
J5-7 Side B: Port 0 through Port 2 headers
J11 Side B: Connects P1.3_B LED and P1.4_B Switch to MCU port pins
J12 Side B: Connects MCU to LIN transceiver (T1)
J19 Side B: Connects decoupling capacitors C41 and C42 for MCU VREF (P0.0)
P3 Side B: DEBUG connector for Debug Adapter interface
pin pull-up, and P1.4_A Switch pull-up.
Rev. 0.1
C8051F540DK
7