Target Board - Silicon Laboratories C8051F99 Series User Manual

C8051F99x

5. Target Board

The C8051F996 Development Kit includes a target board with a C8051F996 device pre-installed for evaluation and
preliminary software development. Numerous input/output (I/O) connections are provided to facilitate prototyping
using the target board. Refer to Figure 8 for the locations of the various I/O connectors. Figure 10 on page 12
shows the factory default shorting block positions.
P1 Expansion connector (96-pin)
P2 Power connector (accepts input from 7 to 15 VDC unregulated power adapter)
P3 USB connector (connects to PC for serial communication)
J1 Enable/Disable VBAT Power LED
J2, J3, J18 Port I/O headers (provide access to Port I/O pins)
J5 Enable/Disable VDD Power LED
J6 Provides an easily accessible ground clip
J7 Connects pin P0.7 (IREF0 Output) to resistor R14 and capacitor C19
J8 Connects P0.2 and P0.3 to switches and P1.5 and P1.3 to LEDs
J9 DEBUG connector for Debug Adapter interface
J10, J11 Selects the power supply source (Wall Power, AAA Battery, or Coin Cell)
J12 Connects Port I/O to UART0 interface
J13 Connects external VREF capacitor to the P0.0/VREF
J14 Connects the PCB ground plane to P0.1/AGND
J15 Connects negative potentiometer (R15) terminal to pin P1.4 or to GND
J16 Connects the potentiometer (R15) wiper to P0.6/CNVSTR
J17 Creates an open in the power supply path to allow supply current measurement
TB1 Analog I/O terminal block
H2 Provides terminal block access to the input and output nodes of J17
SW5 Turns power to the MCU on or off
R15
J16
P1
H1
10
P1.4
J15
TOUCH SENSE SWITCH TOUCH SENSE SWITCH
GND
P1.0
SILICON LABS
PORT2
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J18
F912
U1
J7
PORT1
J3
J6 VDD/DC+
PORT0
J5
Pin 1
Figure 8. C8051F996 Target Board
Rev. 0.2
P1.3 P0.2
SW2
P1.5
USB POWER
P1.1
J8
J11
COIN_CELL
AAA_BAT
J13
WALL_PWR
SW1
J14 +3VD
RESET
IMEASURE
`
J2
J17
H2
VBAT
OFF
ON
SW5
P0.3
SW3
P3
CP
2103
U3
J9
J12
VBAT
Pin 1
Pin 2
J1
P2