Standard Event Status; Figure 5-6 Standard Event Status - Keithley 7002 Instruction Manual

IEEE-488 Reference

5.6.1 Standard event status

The reporting of standard events is controlled by two 16-bit
registers; the Standard Event Status Register and the Stan-
dard Event Status Enable Register. Figure 5-6 shows how
these registers are structured.
To Event Summary
Bit (ESB) of
Status Byte
Register (See
Figure 5-12).
Figure 5-6
Standard event status
5-8
* ESR ? PON
(B15 - B8) (B7)
&
OR
* ESE
PON
(B15 - B8) (B7)
* ESE ?
PON = Power On
URQ = User Request
CME = Command Error
EXE = Execution Error
DDE = Device - Dependent Error
QYE = Query Error
OPC = Operation Complete
& = Logical AND
OR = Logical OR
In general, the occurrence of a standard event sets the appro-
priate bit in the Standard Event Status Register. This register
can be read at any time to determine which, if any, standard
events have occurred. Also, with the proper use of the Stan-
dard Event Status Enable Register, a standard event can set
the Event Summary Bit (ESB) of the Status Byte Register.
This allows the programmer to take advantage of the service
request (SRQ) feature. See paragraph 5.6.8 for details.
URQ CME EXE DDE QYE
(B6) (B5) (B4) (B3) (B2) (B1)
&
&
&
&
URQ CME EXE DDE QYE
(B6) (B5) (B4) (B3) (B2) (B1)
Standard Event
OPC
Status Register
(B0)
&
&
Standard Event
OPC
Status Enable
(B0)
Register