Table 6. Document Revision History - STMicroelectronics STM32F427 Manual

STM32F42xx and STM32F43xx
Revision history
Date
11-Feb-2013
25-Feb-2013
26-Apr-2013
19-Sep-2013
23-Sep-2013

Table 6. Document revision history

Revision
1 Initial release.
Document converted to new template.
2
Added Section 2.8.4: Corruption of data read from the FMC
Added Silicon revision Y.
Removed the reference to 'Cortex-M4F' in the whole document.
Updated Section 2.8.1: Dummy read cycles inserted when reading
synchronous
Added Section 2.1.3: Wakeup sequence from Standby mode when
using more than one wakeup
3
operations to the same register might not be fully taken into account
and Section 2.8.3: FSMC NOR Flash/PSRAM controller
asynchronous access on bank 2 to 4 when bank 1 is in synchronous
mode (CBURSTRW bit is
Removed limitation 2.10.3 SDIO clock divider BYPASS mode may
not work properly. Updated
with wrong data
Added STM32F429xx and STM32F439xx devices.
Removed FSMC limitations.
Added Section 2.3.5: Both SDA and SCL maximum rise time (tr)
violated when VDD_I2C bus higher than ((VDD+0.3) / 0.7)
Updated Section 2.8.5: Interruption of CPU read burst access to an
end of SDRAM
Added Section 2.8.1: Dummy read cycles inserted when reading
synchronous
4
NWAIT signal
initialized FMC_SDRAM
from the FMC,
to an end of SDRAM
controller: asynchronous read access on bank 2 to 4 returns wrong
data when bank 1 is in synchronous mode (BURSTEN bit is set)
Section 2.8.7: FMC dynamic and static banks
Added Figure 1: TFBGA216 top package
top package
Updated workaround in
5 asynchronous read access on bank 2 to 4 returns wrong data when
bank 1 is in synchronous mode (BURSTEN bit is
DocID023833 Rev 5
Changes
memories.
source,
set).
Section 2.9.5: No underrun detection
transmission.
row.
memories, Section 2.8.2: FMC synchronous mode and
disabled, Section 2.8.3: Read access to a non-
bank, Section 2.8.4: Corruption of data read
Section 2.8.5: Interruption of CPU read burst access
row, Section 2.8.6: FMC NOR/PSRAM
view, and Figure 3: LQFP208 top package
Section 2.8.6: FMC NOR/PSRAM controller:
Revision history
Section 2.7.5: Successive write
V.
switching.
view, Figure 2: WLCSP143
view.
set).
and
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35