STMicroelectronics STM32F427 Manual page 3

STM32F42xx and STM32F43xx
2.5.5
2.6 OTG_FS peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6.1
2.6.2
2.6.3
2.6.4
2.7 Ethernet peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.8 FMC peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.8.1
2.8.2
2.8.3
2.8.4
2.8.5
2.8.6
2.8.7
2.9 SDIO peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.9.1
2.9.2
2.9.3
2.9.4
2.9.5
2.10 ADC peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.10.1
2.11 DAC peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.11.1
nRTS signal abnormally driven low after a protocol violation . . . . . . . . 17
Data in RxFIFO is overwritten when all channels are disabled
simultaneously . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
OTG host blocks the receive channel when receiving IN packets and no
TxFIFO is configured . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Host channel-halted interrupt not generated when the channel is
disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Error in software-read OTG_FS_DCFG register values . . . . . . . . . . . . 18
Incorrect layer 3 (L3) checksum is inserted in transmitted IPv6 packets
without TCP, UDP or ICMP payloads . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
The Ethernet MAC processes invalid extension headers in the received
IPv6 frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MAC stuck in the Idle state on receiving the TxFIFO flush command
exactly 1 clock cycle after a transmission completes . . . . . . . . . . . . . . . 19
Transmit frame data corruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Successive write operations to the same register might not be fully
taken into account . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Dummy read cycles inserted when reading synchronous memories . . . 23
FMC synchronous mode and NWAIT signal disabled . . . . . . . . . . . . . . 23
Read access to a non-initialized FMC_SDRAM bank . . . . . . . . . . . . . . 23
Corruption of data read from the FMC . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Interruption of CPU read burst access to an end of SDRAM row . . . . . 24
FMC NOR/PSRAM controller: asynchronous read access on bank 2 to 4
returns wrong data when bank 1 is in synchronous mode
(BURSTEN bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
FMC dynamic and static banks switching . . . . . . . . . . . . . . . . . . . . . . . 25
SDIO HW flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Wrong CCRCFAIL status after a response without CRC is received . . . 25
Data corruption in SDIO clock dephasing (NEGEDGE) mode . . . . . . . . 26
CE-ATA multiple write command and card busy signal management . . 26
No underrun detection with wrong data transmission . . . . . . . . . . . . . . 26
ADC sequencer modification during conversion . . . . . . . . . . . . . . . . . . 27
DMA underrun flag management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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