Table Of Contents - STMicroelectronics STM32F427 Manual

Contents
Contents
1 ARM 32-bit Cortex-M4 with FPU limitations . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Cortex-M4 interrupted loads to stack pointer can cause
erroneous behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 STM32F42xx and STM32F43xx silicon limitations . . . . . . . . . . . . . . . . . 8
2.1 System limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
2.2 IWDG peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.1
2.3 I2C peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.4 I2S peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.1
2.5 USART peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5.1
2.5.2
2.5.3
2.5.4
2/36
Debugging Stop mode and system tick timer . . . . . . . . . . . . . . . . . . . . 10
Debugging Stop mode with WFE entry . . . . . . . . . . . . . . . . . . . . . . . . . 10
Wakeup sequence from Standby mode when using more than
one wakeup source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Full JTAG configuration without NJTRST pin cannot be used . . . . . . . . 11
MPU attribute to RTC and IWDG registers could be managed
incorrectly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Delay after an RCC peripheral clock enabling . . . . . . . . . . . . . . . . . . . . 12
Internal noise impacting the ADC accuracy . . . . . . . . . . . . . . . . . . . . . . 12
Over-drive and Under-drive modes unavailability . . . . . . . . . . . . . . . . . 13
RVU and PVU flags are not reset in STOP mode . . . . . . . . . . . . . . . . . 13
SMBus standard not fully supported . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Start cannot be generated after a misplaced Stop . . . . . . . . . . . . . . . . . 14
Mismatch on the "Setup time for a repeated Start condition" timing
parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Data valid time (t
VD;DAT
Both SDA and SCL maximum rise time (t
higher than ((VDD+0.3) / 0.7) V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
In I2S slave mode, WS level must be set by the external master
when enabling the I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Idle frame is not detected if receiver clock speed is deviated . . . . . . . . 16
In full duplex mode, the Parity Error (PE) flag can be cleared by
writing to the data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Parity Error (PE) flag is not set when receiving in Mute mode
using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Break frame is transmitted regardless of nCTS input line status . . . . . . 17
DocID023833 Rev 5
STM32F42xx and STM32F43xx
) violated without the OVR flag being set . . . . . 14
) violated when VDD_I2C bus
r