Reading The C/S Register; Bit Assignments To The Timer Counter - Tandy 102 Service Manual

(2) Reading the C/S Register
The I/O and timer status can be accessed by reading the contents of the Status register located at
I/O address xxxxx000. The status word format is shown below:
AD7 AD6 AD5 AD4 AD3 AD2 AD1 ADO
TIMER INTE B B BF INTR B INTE A A BF INTR A
Po
rt
A interrupt request
Po
rt
A buffer full
Po
rt
A interrupt enable
Po
rt
B interrupt request
Port B buffer full
Po
rt
B interrupt enable
Timer interrupt. This bit is set high when the timer
reaches TC, and is reset when the C/S register is read or
a hardware reset occurs.
Figure C-9. Reading the C/S Register
(3) PA and PB Registers
These registers may be used as either input or output ports depending on the programmed con-
tents of the C/S register. They may also be used either in the basic mode or in the strobe mode.
I/O address of the PA
register:
xxxxx001
I/O address of the PB
register:
xxxxx010
(4) PC Register
The PC register may be used as an input port, output port or control register depending on the pro-
grammed contents of the C/S register. The I/O address of the PC register is xxxxx011.
(5) Timer
The timer is a 14-bit counter which counts TIMER IN pulses.
The low order byte of the timer register has an I/O address of xxxxx100, and the high order byte of
the register has an I/O address of xxxxx101.
The count length register (CLR) may be preset with two bytes of data. Bits 0 through 13 are as-
signed to the count length: bits 14 and 15 specify the timer output mode. A read operation of the
CLR reads the contents of the counter and the pertinent output mode. The initial value range which
can initially be loaded into the counter is 2 through 3FFF hex. Bit assignments to the timer counter
and possible output modes are shown in the following.
M2 M1 T13 T12 T11 T10 T9 T8
Output mode High order 6 bits of count length
T7 T6 T5 T4 T3 T2 T1 TO
Low order byte of count length
Figure C-10.
Bit Assignments to the Timer Counter
C-11