Functional Block Diagram; Pin Configuration Of 6402 - Tandy 102 Service Manual

C-3. 6402
General Description
The 6402 is a C-MOS LSI subsystem for interfacing the CPU to an asynchronous serial data channel.
The receiver converts serial start, data, parity and stop bits to parallel data verifying proper code
transmission, parity and stop bits. The transmitter converts parallel data into serial form and
automatically, adds start, parity and stop bits. The data word length can be 5, 6, 7 or 8 bits. Parity
may be odd or even. Parity checking and generation can be inhibited. The stop bits may be one or
two or one and one-half when transmitting 5 bits code.
THE
- - - - - - - - - - - - - - -
TBR8(MS1B )
- -
TBRICLSBI
- - - - - - -
TBRE• I
PARITY
RANSMITTER BUFFER REGISTER I
TBRL TRANSMITTER
STOP
LOGIC
RANSMITTER REGISTER START I
TIMING
TRC
(
CONTROL MULTIPLEXER
I
CLSI
CONTROL
CLS2
REGISTER
MR
I
RRC RECEIVER
T NIDNG
DRR
CONTROL
OR*
SFD
STOP PARITY
LOGIC LOGIC
MULTI PLEXER
RECEIVER REGISTER
RECEIVER BUFFER REGISTER
.01
1 tEE AT
JW
BUFFERS
OE# FE PE's +RBRB(MSR3
Figure C- 11. Functional Block Diagram
•+N COt- WWV -•N -.
UWNNU ) JWWWWWWWWOW
J J m ..
m m m m m m m m Q:
W U U cn o. U H H H H l- F- H F- H H
O 01 m W l/1 Q °1 N - O Q1 m l0 111
C7 N ..
Q C1 C1 C1 C'1 C7 C1 t' 1 C7 t'1 N N N N N N N N N
O- N C Q Ul t0 N m Q1 O
8 U O O W 1` W 111 Q M N -W W W O U W *"
Z Z W W W W W W W W W
CL
W O W W O
M
O M M M M M M M M M WWI
MWWWWWWW
Figure C-12. Pin Configuration of 6402
START
LOGIC
RBRICLSBI+
C-13