Tandy 102 Service Manual page 104

Function
Receiver Operation
Data is received in serial form at the RRI. When no data is being received, RRI must remain high.
The data is clocked through the RRC. The clock rate is 16 times the data rate.
[A] A low level on DRR clears the DR line.
[B] During the first stop bit data is transferred from the receiver register to the RBR. If the word is
less than 8 bits, the unused most significant bits will be a low level. The output character is right
justified to the least significant bit RBR1. A high level on OE indicates overruns. An overrun
occurs when DR has not been cleared before the present character was transferred to the RBR.
[C] One clock cycle later, DR is reset to a high level and FE is evaluated. A high level on FE
indicates an invalid stop bit was received, a framing error. A high level on PE indicates a parity
error.
BEGINNING OFFIRST STOP BIT71/2 CLOCK CYCLES
DATA
I
DR
FE
i/2CLOCK
A B C CYCLE
Figure C-13. Receiver Timing