Tandy 102 Service Manual page 93

For RST 7.5, only a pulse is required to set an internal flip-flop which generates the internal interrupt
request. The RST 7.5 request flip-flop remains set until the request is serviced. Then it is reset au-
tomatically. This flip-flop may also be reset by using the SIM instruction or by issuing a RESET IN to
the 80C85A. The RST 7.5 internal flip-flop will be set by a pulse on the RST 7.5 pin even when the
RST 7.5 interrupt is masked out.
The interrupts are arranged in a fixed priority that determines which interrupt is to be recognized if
more than one is pending as follows: TRAP-highest priority, RST 7.5, RST 6.5, RST 5.5, INTR-lowest
priority. This priority scheme does not take into account the priority of a routine that was started by
a higher priority interrupt. RST 5.5 can interrupt an RST 7.5 routine if the interrupts are re-enabled
before the end of the RST 7.5 routine.
The TRAP interrupt is useful for catastrophic events such as power failure or bus error. The TRAP
input is recognized just as any other interrupt but has the highest priority. It is not affected by any
flag or mask. The TRAP input is both edge and level sensitive. The TRAP input must go high and
remain high until it is acknowledged. It will not be recognized again until it goes low, then high
again. This avoids any false triggering due to noise or logic glitches. Figure C-3 illustrates the
TRAP interrupt request circuitry within the 80C85A. Note that the servicing of any interrupt (TRAP,
RST 7.5, RST 6.5, RST 5.5, INTR) disables all future interrupts (except TRAPs) until an El instruction
is executed.
The TRAP interrupt is special in that it disables interrupts, but preserves the previous interrupt
enable status. Performing the first RIM instruction following a TRAP interrupt allows you to deter-
mine whether interrupts were enabled or disabled prior to the TRAP. All subsequent RIM instruc-
tions provide current interrupt enable status. Performing a RIM instruction following INTR or RST
5.5 - 7.5 will provide current Interrupt Enable status, revealing that Interrupts are disabled.
The serial I/O system is also controlled by the RIM and SIM instructions. SID is read by RIM, and
SIM sets the SOD data.
EXTERNAL
TRAP
INTERRUPT
REQUEST TRAP
INSIDE THE 80C85A
RESET IN SCHMITT
TRIGGER -
RESET
TRAP
INTERRUPT
+5V
D CLK
REQUEST
D
F/F
CLEAR
TRAP F.F
INTERNAL
TRAP
ACKNOWLEDGE
Figure C-3. Trap and RESET IN
Basic System Timing
The 80C85A has a multiplexed Data Bus. ALE is used as a strobe to sample the lower 8-bits of ad-
dress on the Data Bus. Figure C-4 shows an instruction fetch, memory read and I/O write cycle (as
would occur during processing of the OUT instruction). Note that during the I/O write and read cy-
cle that the I/O port address is copied on both the upper and lower half of the address.
There are seven possible types of machine cycles. Which of these seven takes place is defined by
the status of the three status lines (IO/M,Si, So) and the three control signals (RD, WR, and INTA).
(See Table C-2.) The status line can be used as advanced controls (for device selection, for exam-
ple), since they become active at the T, state, at the outset of each machine cycle. Control lines RD
and WR become active later, at the time when the transfer of data is to take place, so are used as
command lines.
C-5