Tandy 102 Service Manual page 103

TBR1-8 (Input)
Character data is loaded into the TRANSMITTER BUFFER REGISTER via inputs TBR1-8. For
character formats less than 8 bits the TBR8, 7 and 6 inputs are ignored corresponding to the
programmed word length.
CRL (Input)
A high level on CONTROL REGISTER LOAD loads the control register.
P1
(Input)
A high level on PARITY INHIBIT inhibits parity generation. Parity checking forces PE output low.
SBS (Input)
A high level on STOP BIT SELECT selects 1.5 stop bits for 5 bits character format and 2 stop bits for
the other lengths.
CLS1 , CLS2 (Input)
These inputs program the CHARACTER LENGTH SELECTED (CLS1 low, CLS2 low: 5 bits) (CLS1
high, CLS2 low: 6 bits) (CLS1 low, CLS2 high: 7 bits) (CLS1 high, CLS2 high: 8 bits).
EPE (Input)
When PI is low, a high level on EVEN PARITY ENABLE generates and checks even parity. A low
level selects odd parity.
TRC (Input)
The TRANSMITTER CLOCK is 16X the transmit data rate.
CONTROL WORD
CLS2
L
CLS1
L
PI
L
EPE
L
SBS
L
DATA BITS
5
PARITY BIT
ODD
STOP BITS (S)
1
L L L L H 5
ODD
1.5
L
L L H L 5 EVEN 1
L L L H H 5 EVEN 1.5
L
L
H X
L 5 DISABLED 1
L L H X H 5 DISABLED 1.5
L H L L L 6 ODD 1
L H L L H 6 ODD 2
L H L H L 6 EVEN 1
L H L H H 6 EVEN 2
L H H
X
L 6 DISABLED 1
L H H X H
6
DISABLED 2
H L L L L 7 ODD 1
H L L L H 7 ODD 2
H L L H L 7 EVEN 1
H L
L
H
H
7 EVEN
2
H L H X L 7 DISABLED 1
H L
H
X
H
7 DISABLED
2
H H L L L 8 ODD 1
H H L L H 8 ODD 2
H H L H L 8 EVEN 1
H H L H H 8 EVEN 2
H H H X L 8 DISABLED 1
H
H H
X
H 8
DIsABLED
2
Table C-6. Control Word Format
C-15