Tandy 102 Service Manual page 91

INTR (Input)
INTERRUPT REQUEST: As a general purpose interrupt, it is sampled only during the next to the last
clock cycle of an instruction and during Hold and Halt states. If it is active, the Program Counter
(PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or
CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and
disabled by software. It is disabled by Reset and immediately after an interrupt is accepted.
INTA (Output)
INTERRUPT ACKNOWLEDGE: Used instead of (and has the same timing as ) RD during the instruc-
tion cycle after an INTR is accepted.
RST 5 .5, RST 6.5, RST 7.5 (Input)
RESTART INTERRUPTS: These three inputs have the same timing as INTR, except that they cause
an internal RESTART to be automatically inserted.
The priority of these interrupts is ordered as shown in Table C-1. These interrupts have a higher
priority than INTR. In addition, they may be individually masked out using the SIM instruction.
TRAP (Input)
Trap interrupt is a nonmaskable RESTART interrupt. It is recognized at the same timing as INTR or
RST 5.5 - 7.5. It is unaffected by any mask or Interrupt Disable. It has the highest priority of any in-
terrupt. (See Table C-1.)
RESET IN (Input)
Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops. The data
and address buses and the control lines are 3-stated during RESET and because of the asynchro-
nous nature of RESET, the processor's internal registers and flags may be altered by RESET with
unpredictable results. RESET IN is a Schmitt-triggered input, allowing connection to an R-C net-
work for power-on RESET delay. The CPU is held in the reset condition as long as RESET IN is ap-
plied.
RESET OUT (Output)
Indicates the CPU is being reset. Can be used as a system reset. The signal is synchronized to the
processor clock and lasts an integral number of clock periods.
X1, X2 (Input)
X1 and X2 are connected to a crystal to drive the internal clock generator. X, can also be an external
clock input from a logic gate. The input frequency is divided by 2 to give the processor's internal
operating frequency.
CLK (Output)
Clock Output for use as a system clock. The period of CLK is twice the X1, X2 input period.
SID (Input)
Serial input data line. The data on this line is loaded into accumulator bit 7 whenever a RIM instruc-
tion is executed.
SOD (Output)
Serial output data line . The output SOD is set or reset as specified by the SIM instruction.
Vcc
+5 volt supply.
GND
Ground reference.