Appendix C/Technical Information; C-1. 80C85A - Tandy 102 Service Manual

APPENDIX C/TECHNICAL INFORMATION
C-1. 80C85A
General Description
The 80C85A is a complete 8-bit, parallel central processor implemented in silicon gate C-MOS
technology and compatible with 8085A.
It is designed with the same processing speed and lower power consumption compared with
8085A, thereby offering a high level of system integration.
The 80C85A uses a multiplexed address/data bus. The address is split between the 8-bit address
bus and the 8-bit data bus.
INTA RST6,5 TRAP
INTR RST55 RST 75
SIO SOD
INTERRUPT CONTROL
SERIAL 1/0
CONTROL
BBIT INTERNAL DATA BUS
PGCUMULATOR T EMP REG
INSTRUCTION
(8) (8) REGISTER (8)
FLAG (5)
FLIP-FLOP
B (8) C
(8)
REG REG
ARITHMETIC
LOGIC
INSTRUCTION
DECODER
REG
(8)
REG
E
(8)
UNIT H 8
L (8 )
REGISTER
(ALU)
MACHINE
CYCLE
REG
REG
ARRAY
ENCODING
STACK POINTER
(16)
PROGRAM COUNTER (16)
INCREMENT ER/DECREM
ENTER
ADDRESS LATCH (16)
TIMING AND CONTROL
Xi No CLK
RESET
Xz GEN
1
CONTROL STATUS DMA r --,
CLX OUT ( RD Wk ALE So Si IO/M
t
I HLDA RESET OUT
READY HOLD RESET IN
ADDRESS BUFFER (8)
DATA/ADDRESS BUFFER(8)
A15-A8
ADDRESS BUS
AD? - ADo
ADDRESS/DATA BUS
Figure C-1. Functional Block Diagram
---r X1 I
10 X2
Nq
--- RESET OUT 3
Vcc
HOLD
38 HLDA -
1- SOD
8OC85A 37 CLK(OUT) --
-> SID
36 RESET IN .-^
30
35 READY
.4
TRAP
1
-r .
R
R
ST 75 7
ST65
10/p
S1 --
- 0
RST55
RD --
- 0
INTR 1
31 WR -
Q---- N-TA 1
3 ALE
ADo
So
H AD1 I
28 A15
]No
¢ ADo 14
Ala --
f ADs 15
Ai3
E--- AD4 16
A12
AD5 I
24
A ii Mo.
.F ADs
2
Aio
--
.0
ADo 19
GND 20
Ae
2
AB
--
am.
Figure C-2. Pin Configuration of 80C85A
C-1