Tandy 102 Service Manual page 92

Name
Priority
Address Branched To (1)
When Interrupt Occurs
Type Trigger
TRAP
1
24H
Rising edge and high level
RST 7.5
2 3CH
until sampled.
Rising edge (latched).
RST 6.5 3
34H High level until sampled.
RST 5.5 4 2CH
High level until sampled.
INTR 5
(2) High level until sampled.
Notes : (1) The processor pushes the PC on the stack before branching to the indicated address.
(2) The address branched depends on the instruction provided to the CPU when the inter-
rupt is acknowledged.
Table C-1. Interrupt Priority , Restart Address and Sensitivity
Function
The 80C85A has twelve addressable 8-bit registers. Four can function only as two 16-bit
register pairs. Six others can be used interchangeably as 8-bit registers or a 16-bit register pair.
The 80C85A register set is as follows:
Mnemonic
Register
Contents
ACC or A Accumulator 8-bits
PC Program Counter 16-bit address
BC, DE, HL General-Purpose Register; 8-bit x 6 or 16-bits x 3
data pointer (HL)
SP Stack Pointer
16-bit address
Flags or F Flag Register 5 flag (8-bit space)
The 80C85A uses a multiplexed Data Bus. The address is split between the higher 8-bit Address
Bus and the lower 8-bit Address/Data Bus. During the first T state (clock cycle) of a machine cycle,
the low order address is sent out on the Address/Data Bus. These lower 8-bits may be latched
externally by the Address Latch Enable signal (ALE). During the rest of the machine cycle, the data
bus is used for memory or I/O data.
The 80C85A provides RD, WR, So, Si and IO/M signals for bus control. An Interrupt Acknowledge
signal (INTA) is also provided. Hold and all Interrupts are synchronized with the processor's inter-
nal clock. The 80C85A also provides Serial Input Data (SID) and Serial Output Data (SOD) lines for
a simple serial interface.
In addition to these features, 80C85A has three maskable, vector interrupt pins and one nonmaska-
ble TRAP interrupt.
Interrupt and Serial I/O
The 80C85A has 5 interrupt inputs: INTR, RST 5.5, RST 6.5, RST 7.5, and TRAP. INTR is identical in
function to the 8080A INT. Each of the three RESTART inputs, 5.5, 6.5, and 7.5, has a programma-
ble mask. TRAP is also a RESTART interrupt but it is nonmaskable.
The three maskable interrupts cause the internal execution of RESTART (saving the program
counter in the stack and branching to the RESTART address) if the interrupts are enabled and if the
interrupt mask is not set. The nonmaskable TRAP causes the internal execution of a RESTART vec-
tor independent of the state of the interrupt enable or masks. (See Table C-1.)
There are two different types of inputs in the restart interrupts. RST 5.5 and RST 6.5 are high level-
sensitive like INTR (and INT on the 8080A) and are recognized with the same timing as INTR. RST
7.5 is rising edge-sensitive.
C-4