Tandy 102 Service Manual page 94

A machine cycle normally consists of three T states, with the exception of OPCODE FETCH, which
normally has either four or six T states (unless WAIT or HOLD states are forced by the receipt of
READY or HOLD inputs ). Any T state must be in one of ten possible states , shown in Table C-3.
Machine Cycle
Status Control
_
IO/M Si So RD WR INTA
Opcode Fetch
(OF) 0
1
1 0 1 1
Memory Read (MR) 0
1
0
0 1 1
Memory Write (MW) 0 0 1
1
0
1
I/O Read (IOR)
1 1 0 0 1 1
I/O Write (lOW) 1 0 1 1 0
1
Acknowledge of INTR (INA) 1
1 1 1 1 0
Bus Idle (BI): DAD
ACK. OF
0 1 0
1
1
1
RST, TRAP 1 1 1 1 1 1
HALT TS 0 0 TS TS 1
Table C-2. 80C85A Machine Cycle Chart
Status & Buses Control
Machine State
Si, So IO/M A8 - A15 ADo - ADS RD, WR INTA ALE
T
i
X X
X X 1 1
1 (1)
T2 X X
X X X X 0
TWAIT X X X X X X 0
T3 X X
X
X X X 0
T4
1
0(2)
X TS 1 1
0
T5 1
0(2)
X TS 1 1 0
T6 1
()(2)
X TS
1
1 0
TRESET
X TS
TS TS TS 1 0
THALT
0
TS TS TS TS 1 0
THOLD
X TS TS TS
TS 1
0
0 = Logic "0"
1 =Logic "1"
TS
=High
Impedance
X = Unspecified
Notes : (1)
ALE not
generated during 2nd and 3rd machine cycles of DAD instruction.
(2) IO/M
= 1
during T4-T6 of INA machine cycle.
Table C-3. 80C85A Machine State Chart