Transmitter Operation - Tandy 102 Service Manual

Transmitter Operation
The transmitter section accepts parallel data, formats it and transmits it in serial form on the TRO
terminal.
[A] Data is loaded into the transmitter buffer register from the inputs TBR1 -8 by a logic low on the
TBRL input. Valid data must be present at least t-SET prior to and t-HOLD following the rising
edge of TBRL. If word less than 8 bits are used, only the least significant bits are used. The
character is right justified into the least significant bit, TR1.
[B] The rising edge of TBRL clears TBRE. 0 to 1 clock cycles later, data is transferred to the
transmitter register , THE is cleared , TBRE is set high, and serial data transmission is started.
Output data is clocked by TRC. The clock rate is 16 times the data rate.
[C] A second pulse on TBRL loads data into the transmitter buffer register. Data transfer to the
transmitter register is delayed until transmission of the current character is complete.
[D] Data is automatically transferred to the transmitter register and transmission of that character
begins one clock cycle later.
TBRL
TBRE
THE
1/2
Imo--0TOi CLOCKS ; I•- CLOCK
TRO DATA
A B C
D
END OF
LAST
STOP BIT
Figure C-14. Transmitter Operation