Tandy 102 Service Manual page 90

Functional Pin Description
A8 - Ass (Output, 3-state)
Address Bus: The most significant 8 bits of the memory address or the 8 bits of the I/O address,
3-stated during Hold and Halt modes and during RESET.
ADo - AD7 (Input/Output, 3-state)
Multiplexed Address/Data Bus: Lower 8 bits of the memory address (or I/O address) appear on the
bus during the first clock cycle (T state) of a machine cycle. It then becomes the data bus during
the second and third clock cycles.
ALE (Output)
Address Latch Enable : It occurs during the first clock state of a machine cycle and enables the ad-
dress to latched onto the on -chip latch of the peripherals . The falling edge of ALE is set to guaran-
tee setup and hold times for the address information . The falling edge of ALE can also be used to
strobe the status information. ALE is never 3-stated.
So, S
i
and IO/ M
Machine cycle status:
IO/ M
S
1
So States
IO/ M S
1
So States
0 0 1 Memory write
1 1 1 Interrupt Acknowledge
0 1 0 Memory read 0
0 Halt
. =
3-state
1 0 1 I/O write x
x
Hold (high impedance)
1 1 0 I/O read
x x Reset x= unspecified
0 1 1 Opcode fetch
Si can be used as an advanced R/W status. lO/M, So and S , become valid at the beginning of a ma-
chine cycle and remain stable throughout the cycle. The falling edge of ALE may be used to latch
the state of these lines.
RD (Output, 3-state)
READ control: A low level on RD indicates the selected
memory or I/O device is to be read and that
the Data Bus is available for the data transfer, 3-stated during Hold and Halt modes and during RE-
SET.
WR (Output, 3-state)
WRITE control: A low level on WR indicates the data on the Data Bus is to be written into the select-
ed memory or I/O location. Data is set up at the trailing edge of WR, 3-stated during Hold and Halt
modes and during RESET.
READY (Input)
If READY is high during a read or write cycle, it indicates that the memory or peripheral is ready to
send or receive data. If READY is low, the CPU will wait an integral number of clock cycles for
READY to go high before completing the read or write cycle. READY must conform to specified set-
up and hold times.
HOLD (Input)
HOLD indicates that another master is requesting the use of the address and data buses. The CPU,
upon receiving the hold request, will relinquish the use of the bus as soon as the completion of the
current bus transfer. Internal processing can continue. The processor can regain the bus only after
the HOLD is removed. When the HOLD is acknowledged, the Address, Data, RD, WR, and lO/M
lines are 3-stated.
HLDA (Output)
HOLD ACKNOWLEDGE: Indicates that the CPU has received the HOLD request and that it will re-
linquish the bus in the next clock cycle. HLDA goes low after the Hold request is removed. The
CPU takes the bus one half clock cycle after HLDA goes Ica.