Yamaha RIO3224-D Service Manual page 26

Rio3224-D
R8A02032BG ( X8810A00 ) CPU ( SWX02 )
PIN
OUTER
NAME I/O
NO.
NO.
VSS
1 A1 -
AN2
2 A2 I
AN1
3 A3 I
A4 VSS -
4
A5 RxD1 I
5
A6 SCK1 I
6
A7 UCLK I
7
VSS -
8 A8
I/O
9 A9 FUNC_DM
-
10 A10 VSS
11 A11 HOST_DM I/O
12 A12 POWER_ENB O
13 A13 XTAL O
14 A14 I
EXTAL
A15 -
15 VSS
A16 O
16 CS7N/PJ6
A17 I
17 TRSTN
I
18 A18 TDI
I
19 A19 TCK
-
20 A20 VCCQ
I/O
21 B1 MD15
22 B2 VSS -
23 B3 AN3 I
24 B4 AN0 I
B5 -
25 VSS
B6 O
26 TxD1
B7 O
27 TxD0
B8 -
28 VSS
I/O
29 B9 FUNC_DP
-
30 B10 VSS
I/O
31 B11 HOST_DP
32 B12 SCL I/O
33 B13 VSS -
34 B14 -
VSS
35 B15 O
CS4N/PJ3
B16 O
36 TIOC0A/PJ7
B17 I
37 TESTN
B18 I
38 TMS
-
39 B19 VCCQ
-
40 B20 VCCQ
I/O
41 C1 MD13
42 C2 MD14 I/O
43 C3 VSS -
44 C4 -
VREFADC
45 C5 -
VSSADC
C6 -
46 VSS
C7 I
47 RxD0
C8 -
48 VSS
I
49 C9 VBUS
-
50 C10 VSS
I
51 C11 OVER_CURRENT_N
I/O
52 C12 SDA
53 C13 CS0N O
54 C14 O
CS2N/PJ1
55 C15 O
CS5N/PJ4
C16 I
56 ASEMDN
C17 O
57 TDO
C18 -
58 VCCQ
C19 -
59 VDDPLL
-
60 C20 VDDPLL
I/O
61 D1 MD10
I/O
62 D2 MD11
63 D3 MD12 I/O
64 D4 -
VSS
65 D5 -
VCCADC
66 D6 -
VSS
D7 I
67 RESN
D8 -
68 VCCQ
D9 O
69 PULLUP_ENB
-
70 D10 VCCQ
I
71 D11 UCTL
O
72 D12 EICN
O
73 D13 CS1N/PJ0
74 D14 O
CS3N/PJ2
75 D15 O
CS6N/PJ5
76 D16 I/O
ASEBRKAKN
D17 -
77 VCCQ
D18 -
78 VCCQ
D19 -
79 VSSPLL
26
FUNCTION
Ground
ADC analog input 2
ADC analog input 1
Ground
Serial input 1
External sync. clock input 1
USB external clock input (48 MHz)
Ground
USB function data -
Ground
USB host data -
USB voltage enable
Crystal oscillator output
Crystal oscillator input (16.9344 MHz)
Ground
SH2A-CPU chip select 7
JTAG test reset input
JTAG test data input
JTAG test clock input
Power supply +3.3 V
Wave memory data bus 15
Ground
ADC analog input 3
ADC analog input 0
Ground
Serial output 1
Serial output 0
Ground
USB function data +
Ground
USB host data +
E bus (I2C) clock input/output (5V compatible)
Ground
SH2A-CPU chip select 4
PWM output
Test input
JTAG test mode select input
Power supply +3.3 V
Wave memory data bus 13
Wave memory data bus 14
Ground
ADC reference power supply +3.3 V
ADC analog ground
Ground
Serial input 0
Ground
USB cable connection monitor (5V compatible)
Ground
USB overcurrent detection (5V compatible)
E bus (I2C) data input/output (5V compatible)
SH2A-CPU chip select 0
SH2A-CPU chip select 2
SH2A-CPU chip select 5
Debug mode configuration
JTAG test data output
Power supply +3.3 V
PLL analog power supply +1.2 V
Wave memory data bus 10
Wave memory data bus 11
Wave memory data bus 12
Ground
ADC analog power supply +3.3 V
Ground
Hardware reset
Power supply +3.3 V
USB pull-up enable
Power supply +3.3 V
USB output control
E bus reset output
SH2A-CPU chip select 1
SH2A-CPU chip select 3
SH2A-CPU chip select 6
Emulator break
Power supply +3.3 V
PLL analog ground
PIN
OUTER
NAME I/O
NO.
NO.
80
D20 VSSPLL -
81
E1 MD6 I/O
82
E2 MD7 I/O
83
E3 MD8 I/O
84
MD9 I/O
E4
85 VDD -
E5
86 VDD -
E6
87 VSS
E7 -
88 VCCQ
E8 -
89 VSS
E9 -
90
E10 VCCQ -
91
E11 VCCQ -
92
E12 VSS -
93
E13 VCCQ -
94
VSS -
E14
95 VDD -
E15
96 VDD -
E16
97 D31/PF7
E17 I/O
98 D30/PF6
E18 I/O
99 D29/PF5
E19 I/O
100 D28/PF4
E20 I/O
101
F1 MD2 I/O
102
F2 MD3 I/O
103
F3 MD4 I/O
104
MD5 I/O
F4
105
VDD -
F5
106 VDD -
F16
107 D27/PF3 I/O
F17
108 D26/PF2
F18 I/O
109 D25/PF1
F19 I/O
110 D24/PF0
F20 I/O
111
G1 MA2 O
112
G2 MA1 O
113
G3 MD0 I/O
114
G4 MD1 I/O
115
VSS -
G5
116 VSS -
G16
117 D23/PE7 I/O
G17
118 D22/PE6
G18 I/O
119 D21/PE5
G19 I/O
120 D20/PE4
G20 I/O
121
H1 MA6 O
122
H2 MA5 O
123
H3 MA4 O
124
H4 MA3 O
125
VCCQ -
H5
126
VCCQ -
H16
127 D19/PE3 I/O
H17
128 D18/PE2 I/O
H18
129 VCCQ
H19 -
130 VCCQ
H20 -
131 MA10
J1 O
132
J2 MA9 O
133
J3 MA8 O
134
J4 MA7 O
135
J5 VSS -
136
VSS -
J9
137 VSS -
J10
138 VSS -
J11
139 VSS
J12 -
140 VSS
J16 -
141 D17/PE1
J17 I/O
142
J18 D16/PE0 I/O
143
J19 CKOEN I
144
J20 CKIO O
145
K1 MA14 O
146
MA13 O
K2
147 MA12 O
K3
148 MA11 O
K4
149 VDD
K5 -
150 VSS
K9 -
151 VSS
K10 -
152 VSS
K11 -
153
K12 VSS -
154
K16 VDD -
155
K17 CKE O
156
D15 I/O
K18
157
VSS -
K19
158 VSS -
K20
DNTSB: IC001
FUNCTION
PLL analog ground
Wave memory data bus 6
Wave memory data bus 7
Wave memory data bus 8
Wave memory data bus 9
Power supply +1.2 V
Ground
Power supply +3.3 V
Ground
Power supply +3.3 V
Ground
Power supply +3.3 V
Ground
Power supply +1.2 V
SH2A-CPU data bus 31
SH2A-CPU data bus 30
SH2A-CPU data bus 29
SH2A-CPU data bus 28
Wave memory data bus 2
Wave memory data bus 3
Wave memory data bus 4
Wave memory data bus 5
Power supply +1.2 V
SH2A-CPU data bus 27
SH2A-CPU data bus 26
SH2A-CPU data bus 25
SH2A-CPU data bus 24
Wave memory address bus 2
Wave memory address bus 1
Wave memory data bus 0
Wave memory data bus 1
Ground
SH2A-CPU data bus 23
SH2A-CPU data bus 22
SH2A-CPU data bus 21
SH2A-CPU data bus 20
Wave memory address bus 6
Wave memory address bus 5
Wave memory address bus 4
Wave memory address bus 3
Power supply +3.3 V
SH2A-CPU data bus 19
SH2A-CPU data bus 18
Power supply +3.3 V
Wave memory address bus 10
Wave memory address bus 9
Wave memory address bus 8
Wave memory address bus 7
Ground
SH2A-CPU data bus 17
SH2A-CPU data bus 16
Clock output control for SDRAM
Clock output for SDRAM
Wave memory address bus 14
Wave memory address bus 13
Wave memory address bus 12
Wave memory address bus 11
Power supply +1.2 V
Ground
Power supply +1.2 V
Clock enable for SDRAM
SH2A-CPU data bus 15
Ground