Initiator Asynchronous Receive; Target Asynchronous Send - LSI LSI53C1000 Technical Manual

Pci to ultra160 scsi controller
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Table 6.40

Initiator Asynchronous Receive

Symbol
Parameter
t
SACK/ asserted from SREQ/ asserted
1
t
SACK/ deasserted from SREQ/ deasserted
2
t
Data setup to SREQ/ asserted
3
t
Data hold from SACK/ asserted
4
Table 6.41

Target Asynchronous Send

Symbol
Parameter
t
SREQ/ deasserted from SACK/ asserted
1
t
SREQ/ asserted from SACK/ deasserted
2
t
Data setup to SREQ/ asserted
3
t
Data hold from SACK/ asserted
4
Figure 6.36 Initiator Asynchronous Receive
SREQ/
SACK/
t
3
SD[15:0]/,
SDP[1:0]/
Figure 6.37 Target Asynchronous Send
SREQ/
SACK/
t
SD[15:0]/,
SDP[1:0]/
SCSI Timing Diagrams
Min
t
n
2
t
1
n
Valid n
Min
5
5
55
0
n
t
1
n
3
Valid n
Max
5
5
0
0
n + 1
n + 1
t
4
Valid n + 1
Max
n + 1
t
2
n + 1
t
4
Valid n + 1
Units
ns
ns
ns
ns
Units
ns
ns
ns
ns
6-63

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