Universal Asynchronous Receiver/Transmitter (Uart); Zcr Circuit Diagram For The Lsisas1068 - LSI LSISAS1068 Technical Manual

Figure 2.7

ZCR Circuit Diagram for the LSISAS1068

ZCR PCI
Slot
Int A/ (A6)
Int B/ (B7)
Int C/ (A7)
Int D/ (B8)
Vdd
4.7 kΩ
TDI (A4)
GNT/ (A17)
IDSEL (A26)
AD21 (B29)
Vdd
0.1 kΩ
Host System
Int A/
Int B/
Int C/
Int D/
AD21
AD19
Note: To maintain proper interrupt mapping, select the address line for use as IDSEL on the LSISAS1068 to be +2
address lines above IDSEL on ZCR slot.
2.8

Universal Asynchronous Receiver/Transmitter (UART)

2-26
Vdd
0.1 kΩ
Vdd
4.7 kΩ
220 Ω
The LSISAS1068 provides an industry standard UART interface. The
UART performs serial-to-parallel conversion on data characters received
from a peripheral device or modem, and parallel-to-serial conversion on
data characters received from the CPU. The CPU has access to UART
status at any time during functional operation. The status information
includes the type and condition of the transfer operations being
performed by the UART, and any error conditions such as parity, overrun,
framing, or break interrupt.
The LSISAS1068 UART is compatible with the standard 16550 UART,
with the following exceptions:
•
Uses speed sense logic to automatically determine the speed of a
connected modem.
Functional Description
Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
LSISAS1068
ALT_INTA/
ZCR_EN/
ALT_GNT/
IDSEL