Digital Input - Timing; Digital Output; Digital Output - General Info; Digital Output - Signal Levels - XIMEA xiQ series Technical Manual

3.8.3.5. Digital Input – Timing
Typical measured input delay between Digital Input to FPGA Input
Measurements of input delays:
Edge Type Input Voltage [V]
Rising
Rising
Falling
Falling
table 3-25, digital input, timing
Note:
• Measured at: Ambient Temperature 25°C
3.8.4.

Digital Output

3.8.4.1.

Digital Output - General info

Item
Indicator
Output port type
Protection
Protection circuit
Effect of incorrect output terminal connection
Inductive loads
Maximal output dropout
table 3-26, digital output, general info
3.8.4.2. Digital Output – signal levels
Output levels definition
State Open Collector Switch State
On (1) ON - Transistor is conducting
Off (0) OFF - Transistor is not conducting
table 3-27, digital output, signal levels
Maximum sink current: 25 mA
Maximum open circuit voltage: 24V
xiQ - Technical Manual Version 1.0
Typ. delay [μs]
15 1.4
20 0.6
15 5.3
20 7.8
Parameter / note
Yes, must be configured by user to Status 1 LED
Open collector NPN
short-circuit / over-current / Reverse voltage
PTC Resettable Fuse
Not protected against reverse voltage connection
no
1.8V, Sink current 25mA
R [Ohm]
max. 160
min 100 k
Conditions
For output > 5mA
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