Omron SYSMAC CS1 Operation Manual page 42

Specifications
Item
EM Area
Data Registers
Index Registers
Task Flag Area
Trace Memory
File Memory
Function Specifications
Item
Constant cycle time
Cycle time monitoring
I/O refreshing
Timing of special refreshing
for CPU Bus Units
I/O memory holding when
changing operating modes
32K words per bank, 13 banks max.: E0_00000 to EC_32767 max.
(Not available on some CPU Units.)
Used as a general-purpose data area for reading and writing data in
word units (16 bits). Words in the EM Area maintain their status when
the PLC is turned OFF or the operating mode is changed.
The EM Area is divided into banks, and the addresses can be set by
either of the following methods.
Changing the current bank using the EMBC(281) instruction and
setting addresses for the current bank.
Setting bank numbers and addresses directly.
EM data can be stored in files by specifying the number of the first
bank.
DR0 to DR15
Store offset values for indirect addressing. One register is 16 bits (1
word).
CS1 CPU Units: Data registers used independently in each task.
CS1-H CPU Units: Setting to use data registers either independently in
each task or to share them between tasks.
IR0 to IR15
Store PLC memory addresses for indirect addressing. One register is
32 bits (2 words).
CS1 CPU Units: Index registers used independently in each task.
CS1-H CPU Units: Setting to use index registers either independently
in each task or to share them between tasks.
32 (TK0000 to TK0031)
Task Flags are read-only flags that are ON when the corresponding
cyclic task is executable and OFF when the corresponding task is not
executable or in standby status.
4,000 words (trace data: 31 bits, 6 words)
Memory Cards: Compact flash memory cards can be used (MS-DOS
format).
EM file memory: Part of the EM Area can be converted to file memory
(MS-DOS format).
1 to 32,000 ms (Unit: 1 ms)
When a parallel processing mode is used for a CS1PC-PCI01H-DRM CS1 Board, the
cycle time for executing instructions is constant.
Possible (Unit stops operating if the cycle is too long): 1 to 40,000 ms (Unit: 10 ms)
When a parallel processing mode is used for a CS1PC-PCI01H-DRM CS1 Board, the
instruction execution cycle is monitored. The CS1 Board's CPU Unit Module
operation will stop if the peripheral servicing cycle time exceeds 2 s (fixed).
Cyclic refreshing, immediate refreshing, refreshing by IORF(097).
IORF(097) refreshes I/O bits allocated to Basic I/O Units and Special I/O Units.
With the CS1PC-PCI01H-DRM CS1 Boards, the CPU BUS UNIT I/O REFRESH
(DLNK(226)) instruction can be used to refresh bits allocated to CPU Bus Units in the
CIO and DM Areas.
Data links for Controller Link Units and SYSMAC LINK Units, remote I/O for
DeviceNet Units, and other special refreshing for CPU Bus Units is performed at the
following times:
CS1PC-PCI01-DRM CS1 Boards: I/O refresh period
CS1PC-PCI01H-DRM CS1 Boards: I/O refresh period and when the CPU BUS UNIT
I/O REFRESH (DLNK(226)) instruction is executed
Depends on the ON/OFF status of the IOM Hold Bit in the Auxiliary Area.
Specification
Specification
Section 1-11
Reference
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