Yamaha CRX-E500 Service Manual page 32

CDC-E500
Pin No. Name I/O
47 DSLF I/O
48 PLLF I/O
49 VCOF I/O
50 AVDD2 I
51 AVSS2 I
52 EFM O
53 PCK/ O
RESY
54 FLAG O
55 CRC O
56 XSEL I
57 VSS I
58 X1 I
59 X2 O
60 VDD I
61 VCOF2 O
62 AVSS1 O
63 OUT1C O
64 OUT1D O
65 OUT2D O
66 OUT2C O
67 AVDD1 I
68 DEMPO O
69 CK384 O
70 IOSEL I
71 TEST I
72 SBCK2 I
73 SUBC O
74 SBCK I
75 CLDCK O
76 IPFLAG O
77 DEMPI I
/TEST2
78 SDATI I
79 LRCKI I
80 BCKI I
* The PEM is the abbreviation for the Pulse Edge Modulation.
32
Loop filter terminal for DSL
Loop filter terminal for PLL
Loop filter terminal for VCO
Power supply for analog circuit (for AD of DSL, PLL, DA output blocks)
GND for analog circuit (for AD of DSL, PLL, DA output blocks)
EFM signal output
With command defaulted : PLL extract clock output PCK when IOSEL=H, frame re-synchronous signal RESY when IOSEL=L
These settings can be reversed by command (RESY when IOSEL=H).
Flag signal output
Sub-code CRC check result output (H : OK, L : NG)
L : Normal mode
H : • For internal master clock, VCO2 output clock for jitter adsorbing PLL is used instead of Xtal
oscillation output (X2).
• VCO2 is always fixed to oscillation mode regardless of VCO2 oscillation stop command or
resetting (/RST=L) and Xtal oscillation is stopped.
GND for oscillation circuit
Crystal oscillation circuit input terminal
Crystal oscillation circuit output terminal
Power supply for oscillation circuit
PLL loop filter terminal for jitter adsorption
GND for audio DAC
PEM output terminal 1C
PEM output terminal 1D
PEM output terminal 2D
PEM output terminal 2C
Power supply terminal for audio DAC
Deemphasis detect signal output
384fs clock output (At the CK384 pin, output does not stop while /RST=L.)
Xtal system when command is defaulted. Signal processing system when command is switched
Mode selecting terminal
Test mode setting terminal (Normal : H)
Sub-code data read clock input
Sub-code serial output (SBCK effective) when command is defaulted.
PACK data usable (SBCK2 effective) when command is switched
Clock input for sub-code serial output (with pull-up resistor)
Sub-code frame clock signal output when command is defaulted (fCLDCK=7.35kHz)
PACK synchronous signal when command is switched
Interpolation flag signal output (H : INTERPOLATION)
When IOSEL=H, L : NORMAL H : TEST2
Emphasis control in accordance with DEMP0
When IOSEL=L, external DEMP1 input terminal
For emphasis control, DEMP0, OR of DEMP1, DEMP1, forced OFF or forced ON is selected by command.
When command is defaulted, DEMP0 and OR of DEMP1
SRDATA input (effective only when IOSEL=L)
LRCK input (effective only when IOSEL=L) H : Lch data, L : Rch data
BCK input (effective only when IOSEL=L)
Function
(+5)
(+5)
(GND)
(NC)
(NC)
(NC)
(NC)
(GND)
(+5)
(GND)
(NC)
(NC)
(+5)
(+5)
(NC)
(NC)
(GND)
(NC)
(NC)
(NC)