Fujitsu MAA3182FC Series Manual page 192

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a. RLEC (report log exception condition) (not supported)
Since the IDD does not support the LOG SELECT command, "1" cannot be specified in
this field. Even if "1" is specified, the IDD will disregard it.
This bit controls operations in cases where the accumulated value log parameter reaches
the maximum value.
When "0" is specified in this bit, the IDD executes the command which is issued next
normally.
When "1" is specified in this bit, the IDD reports a CHECK CONDITION status (UNIT
ATTENTION [=6] / Log counter at maximum [5B-02]).
b. Queue algorithm qualifier
This parameter controls the execution order algorithm of a command issued together with
a SIMPLE QUEUE TAG message.
When "0" is specified in this parameter, the IDD executes commands queued from each
INIT in the order in which they were received. However, the command execution order
for the READ, READ EXTENDED and PRE-FETCH commands may be changed.
When "1" is specified in this parameter, the IDD executes queued commands by the
method selected by the IDD. At this time, the INIT must verify the correctness of the data
through appropriate commands and QUEUE TAG messages.
c. QErr (queue error management)
This bit controls processing of commands queued after a sense hold state is canceled when
the IDD is in the sense hold state.
When "0" is specified in this bit, the IDD, when it has been in any one of various sense
hold states, then that sense hold state is cleared, continues executing the commands which
are queued by normal methods.
When "1" is specified in this bit, the IDD, when it has been in any one of various sense
hold states, then that sense hold state is cleared, clears the commands which are queued.
At this time, the IDD generates a UNIT ATTENTION condition (UNIT ATTENTION [=6]
/ Command cleared by another initiator = [2F-00]) for each of the INITs that issued the
commands which were cleared.
d. DQue (disable queuing)
This bit specifies whether the IDD will execute processing of tagged commands or not.
When "0" is specified in this bit, the IDD permits tagged queuing processing.
C141-E054-02EN
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