Digital Control Loop - Analog Devices ADP1055-EVALZ User Manual

UG-710

DIGITAL CONTROL LOOP

Control Loop Configuration
The control loop configuration procedures can be shown as a
series of three steps.
1. The board parameters are set, including topology, turn
ratio of main transformer, output LC filter and output
voltage feedback network. Using this inform-ation, the
ADP1055 generates the Bode plots of LC filter and
feedback network.
2. The switching frequency is determined in the PWM
settings window. Changing of the switching frequency
changes the low frequency gain and the third pole position.
3. You can start to place the zeros and poles, and set the low
frequency gain and high frequency gain of the Type-III
compensator, based on the stability rules.
Using the loop analyzer, you can validate the programmed
control loop as shown in Figure 78. For an easy test on the
control loop, the signal from loop analyzer can be injected in
J11and TP26 in the schematic.
Figure 77. Digital Filter Settings Window
The double update rate feature of the
increases the ability to push the bandwidth to higher limits
while still retaining a good phase margin.
ADP1055 greatly
Rev. B | Page 22 of 43
ADP1055-EVALZ User Guide
Figure 78. Control Loop Test by AP300 Loop Analyzer
(Double Update Rate Enabled)
Crossover Frequency is 5.41kHz
Phase Margin is 60°
Gain Margin is 22 dB
Figure 79. Digital Filter Settings Window
Optimized Filter to Provide Better Crossover Frequency
Figure 80. Control Loop Test by AP300 Loop Analyzer
(Double Update Rate Enabled)
Crossover Frequency is 9.08 kHz
Phase Margin is 58°
Gain Margin is 22 dB