Aaeon MB-562 Manual page 90

Set this item to Enabled to pre-defined values for DRAM, cache
timing according to CPU type & system clock. Thus, each item value
may display differently depending on your system configurations.
When this item is enabled, the pre-defined items will become SHOW-
ONLY .
This item allows you to select between two methods of chipset NA#
asserted during CPU write cycle/CPU line fills, Enabled and Disabled.
DRAM must continually be refreshed or it will lose its data. Normally,
DRAM is refreshed entirely as the result of a single request. This
option allows you to determine the number of CPU clocks allocated for
the Row Address Strobe to accumulate its charge before the DRAM is
refreshed. If insufficient time is allowed, refresh may be incomplete
and data lost.
When DRAM is refreshed, both rows and columns are addressed
separately. This setup item allows you to determine the timing of the
transition from Row Address Strobe (RAS) to Column Address Strobe
(CAS).
Set this option to Enabled to give priority to posted messages from the
CPU to PCI bus.
Set this option to Enabled to allow write instructions to be combined in
PCI burst mode. The settings are Enabled or Disabled.
This item allows you to select the ISA bus clock PCICLK/3 OR
PCICLK/4.
82 MB-562 User's Manual