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2.6
Reset Block Diagram
DSPC-8682 reset mechanism is shown in Figure 9. DSPC-8682 Reset Block Diagram with below
description of the reset sequence on DSPC-8682.
The FPGA on the card will do the power-on sequence and make all power rails on the card
be ready.
The FPGA waits for the PWROK on PCI-E golden finger (PCIE_GF_RST#) asserted.
After PCI-E PWROK asserted as well as all the power on the card valid, the FPGA will
de-assert PEX8748_PCIE_PERST# of PEX8748, the PCI-E switch, 5482S_PHY_RST# of
BCM5482s, the PHY chip, CPS1616_RST# of CPS-1616, SRIO switch, and DSP[0:7]_RESET# on
eight DSP chips.
To wait for 5mS, the FPGA de-assert the DSP_POR# to eight DSPs.
To wait for 5mS, the FPAG de-assert the DSP_RESETFULLz to eight DSPs.
During DSP_RESETFULLz de-asserted, the DSP straps the boot configurations on its own
GPIO pins driven by the FPAG.
1ms later after DSP_RESETFULLz de-asserted, the FPGA will set the GPIO pins on the FPGA
side at input, after that, the reset sequence on DSPC-8682 is completed then.
PEX8748_PCIE_RST#
PEX8748
CPS1616_RST#
CPS1616
5482S_PHY_RST#
BCM5482S
PCIE_GF_RST#
DSP_RESETFULL#
FPGA
DSP[0..7]_RESET#
DSP_POR#
XC3S200AN
Figure9: DSPC-8682 Reset Block Diagram
Page
22
of
47
TI
TMS320C6678
DSP0 ~ DSP7
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