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2.11 PCI-E interface
DSPC-8682 adopts a star topology to link host platform with two-lane PCIE interface via a PCI-E Gen3
switch, PEX8748. One PCI-E Gen2 port is designed with two Lanes (supports up to 5G baud per lane)
connected to each DSP.
With PEX8748, it can support up to 12-ports PCI Express switch with 48 lanes of integrated on-chip
SerDes and provide an aggregated bandwidth of up to 768 GT/s. (8.0 GT/s/Lane x 48 SerDes x 2 (full
duplex))
Below table describes the port mapping of PEX8748 on DSPC-8682 while below figure describes the
PCI-E interconnection on DSPC-8682.
Port
0
1
2
8
9
10
11
16
17
Figure12: Serial RapidIO Ring
Function
Connects to Host computer (Root Complex) by PCI-E X8
Connects to DSP0 through PCI-E X2 interface
Connects to DSP1 through PCI-E X2 interface
Connects to DSP2 through PCI-E X2 interface
Connects to DSP3 through PCI-E X2 interface
Connects to DSP4 through PCI-E X2 interface
Connects to DSP5 through PCI-E X2 interface
Connects to DSP6 through PCI-E X2 interface
Connects to DSP7 through PCI-E X2 interface
Table 4: PCI-E port mapping on PEX8748
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