Interface Timing; Timing Characteristics - Advantech IDK-1119R-35SXA1E User Manual

Note1 Input signals of odd and even clock shall be the same timing. And start from
the left side.
Note2 Input signals of add and even clock shall be the same timing
Note3 Please follow VESA.
3.4

Interface Timing

3.4.1

Timing Characteristics

Table 3.2: Timing Characteristics
Signal Parameter
Period
Vertical
Active
Section
Blanking
Period
Horizontal
Active
Section
Blanking
Clock Period
Frequency
Frame Rate Frequency
Note DE mode only.
IDK-1119R User Manual
Symbol Min.
Tv 1032
Tdisp(v) 1024
Tbp(v)+Tfp(v)+ 8
PWvs
Th 780
Tdisp(h) 640
Tbp(h)+Tfp(h)+ 140
PWhs
Tclk 22.2
Freq. 45
1/Tv 50
14
Typ. Max. Unit
1066 1150 Th
1024 1024 Th
42 126 Th
844 2047 Tclk
640 640 Tclk
204 - Tclk
18.52 14.81 ns
54 67.5 MHz
60 75 Hz