Signal Description - Advantech IDK-1119R-35SXA1E User Manual

3.3

Signal Description

The module using a pair of LVDS receiver SN75LVDS82 (Texas Instruments) or com-
patible. LVDS is a differential signal technology for LCD interface and high speed
data transfer device. Transmitter shall be SN75LVDS83 (negative edge sampling) or
compatible. The first LVDS port (RxOxxx) transmits odd pixels while the second
LVDS port (RxExxx) transmits even pixels.
Table 3.1: Signal Description
Pin No. Singal Name Description
1 RxOIN0-
2 RxOIN0+
3 RxOIN1-
4 RxOIN1+
5 RxOIN2-
6 RxOIN2+
7 VSS
8 RxOCLKIN-
9 RxOCLKIN+
10 RxOIN3-
11 RxOIN3+
12 RxEIN0-
13 RxEIN0+
14 VSS
15 RxEIN1-
16 RxEIN1+
17 VSS
18 RxEIN2-
19 RxEIN2+
20 RxECLKIN-
21 RxECLKIN+
22 RxEIN3-
23 RxEIN3+
24 VSS
25 VSS
26 NC
27 VSS
28 VCC
29 VCC
30 VCC
Negative LVDS differential data input (Odd data)
Positive LVDS differential data input (Odd data)
Negative LVDS differential data input (Odd data)
Positive LVDS differential data input (Odd data)
Negative LVDS differential data input (Odd data, H-Sync,V-
Sync,DSPTMG)
Positive LVDS differential data input (Odd data, H-Sync,V-
Sync,DSPTMG)
Power Ground
Negative LVDS differential clock input (Odd clock)
Positive LVDS differential clock input (Odd clock)
Negative LVDS differential data input (Odd data)
Positive LVDS differential data input (Odd data)
Negative LVDS differential data input (Even data)
Positive LVDS differential data input (Even data)
Power Ground
Negative LVDS differential data input (Even data)
Positive LVDS differential data input (Even data)
Power Ground
Negative LVDS differential data input (Even data)
Positive LVDS differential data input (Even data)
Negative LVDS differential clock input (Even clock)
Positive LVDS differential clock input (Even clock)
Negative LVDS differential data input (Even data)
Positive LVDS differential data input (Even data)
Power Ground
Power Ground
Do not connect ( for AUO test)
Power Ground
+5.0V Power Supply
+5.0V Power Supply
+5.0V Power Supply
13 IDK-1119R User Manual