Mmu Control; Invalidate (Flush) Operation; Enabling/Disabling; Valid Mmu & Data/Mini-Data Cache Combinations - Intel IXP45X Developer's Manual

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Intel XScale Processor—Intel
Table 8. Valid MMU & Data/Mini-Data Cache Combinations
3.1.3

MMU Control

3.1.3.1

Invalidate (Flush) Operation

The entire instruction and data TLB can be invalidated at the same time with one
command or they can be invalidated separately. An individual entry in the data or
instruction TLB can also be invalidated. See
a listing of commands supported by the Intel XScale processor.
Globally invalidating a TLB will not affect locked TLB entries. However, the invalidate-
entry operations can invalidate individual locked entries. In this case, the locked
contents remain in the TLB, but will never "hit" on an address translation. Effectively,
creating a hole is in the TLB. This situation may be rectified by unlocking the TLB.
3.1.3.2

Enabling/Disabling

The MMU is enabled by setting bit 0 in coprocessor 15, register 1 (Control Register).
When the MMU is disabled, accesses to the instruction cache default to cacheable
accesses and all accesses to data memory are made non-cacheable.
A recommended code sequence for enabling the MMU is shown in
page 74.
August 2006
Order Number: 306262-004US
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IXP45X and Intel IXP46X Product Line of Network Processors
MMU Data/mini-data Cache
Off
On
On
Off
Off
On
Table 21, "TLB Functions" on page 105
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
for
Example 1 on
Developer's Manual
73