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USB 2.0 Host Controller—Intel
Figure 73.
siTD Scheduling Boundary Examples
Case 1
4
5
6
7
0
B-Frame
Y-1
5
6
7
0
1
H-Frame
Y-1
Each case is described below:
• Case 1: One siTD is sufficient to describe and complete the isochronous split
transaction because the whole isochronous split transaction is tightly contained
within a single H-Frame.
• Case 2a, 2b: Although both INs and OUTs can have these footprints, OUTs always
take only one siTD to schedule. However, INs (for these boundary cases) require
two siTDs to complete the scheduling of the isochronous split transaction
used to always issue the start-split and the first N complete-splits. The full-speed
transaction (for these cases) can deliver data on the full-speed bus segment during
micro-frame 7 of H-Frame
are scheduled using siTD
must use the buffer pointer from siTD
reach siTD
rules for when to use the back pointer are described is
Complete Split" on page
Software must apply the following rules when calculating the schedule and linking the
schedule data structures into the periodic schedule:
• Software must ensure that an isochronous split-transaction is started so that it will
complete before the end of the B-Frame.
• Software must ensure that for a single full-speed isochronous endpoint, there is
never a start-split and complete-split in H-Frame, micro-frame 1. This is mandated
as a rule so that case 2a and case 2b can be discriminated. According to the core
USB specification, the long isochronous transaction illustrated in Case 2b, could be
scheduled so that the start-split was in micro-frame 1 of H-Frame N and the last
complete-split would need to occur in micro-frame 1 of H-Frame N+1. However, it
is impossible to discriminate between cases 2a and case 2b, which has significant
impact on the complexity of the host controller.
9.14.12.3.2 Tracking Split Transaction Progress for Isochronous Transfers
To correctly maintain the data stream, the host controller must be able to detect and
report errors where device to host data is lost. Isochronous endpoints do not employ
the concept of a halt on error, however the host is required to identify and report per-
packet errors observed in the data stream. This includes schedule traversal problems
(skipped micro-frames), timeouts and corrupted data received.
August 2006
Order Number: 306262--, Revision: 004US
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
Case 2a
1
2
3
4
5
6
B-Frame
Y
2
3
4
5
6
7
H-Frame
Y
siTD
X
Back Pointer
Y+1
X+2
from H-Frame
X+1
Y+2
476.
Case 2b
7
0
1
2
3
B-Frame
0
1
2
3
4
H-Frame
Y+1
siTD
X+1
, or micro-frame 0 of H-Frame
(not shown). The complete-splits to extract this data
.
The only way for the host controller to
X+1
is to use siTD
's back pointer. The host controller
X+2
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Full-Speed
Transaction
4
5
6
7
0
1
B-Frame
Y+1
5
6
7
0
1
2
H-Frame
Y+2
.
The complete splits
Y+2.
"Periodic Isochronous - Do
Developer's Manual
2
Y+2
3
B4521-01
siTD
is
X
471
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