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USB 2.0 Host Controller—Intel
Table 141.
PORTSCx - Port Status Control[1:8] (Sheet 3 of 4)
Field
HSP
PR
SUSP
FPR
August 2006
Order Number: 306262--, Revision: 004US
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
High-Speed Port — Read Only. Default = 0b.
When the bit is one, the host connected to the port is in high-speed mode and if set to zero, the
host connected to the port is not in a high-speed mode.
Note:
HSP is redundant with PSPD(27:26) but will remain in the design for compatibility.
This bit is not defined in the EHCI specification.
This implementation does not support HS mode of operation.
Port Reset
This field is zero if Port Power() is zero.
In Host Mode: Read/Write.
0 = Port is not in Reset.
1 = Port is in Reset.
Default 0.
When software writes a one to this bit the bus-reset sequence as defined in the USB
Specification Revision 2.0 is started. This bit will automatically change to zero after the reset
sequence is complete. This behavior is different from EHCI where the host controller driver is
required to set this bit to a zero after the reset duration is timed in the driver.
Suspend
In Host Mode: Read/Write.
0 = Port not in suspend state.
1 = Port in suspend state.
Default=0.
Port Enabled Bit and Suspend bit of this register define the port states as follows:
Bits [Port Enabled, Suspend]Port State
0x
Disable
10
Enable
11
Suspend
When in suspend state, downstream propagation of data is blocked on this port, except for port
reset. The blocking occurs at the end of the current transaction if a transaction was in progress
when this bit was written to 1. In the suspend state, the port is sensitive to resume detection.
Note that the bit status does not change until the port is suspended and that there may be a
delay in suspending a port if there is a transaction currently in progress on the USB.
The host controller will unconditionally set this bit to zero when software sets the Force Port
Resume bit to zero. A write of zero to this bit is ignored by the host controller.
If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a
zero) the results are undefined.
This field is zero if Port Power() is zero in host mode.
Force Port Resume —Read/Write.
0 = No resume (K-state) detected/driven on port.
1 = Resume detected/driven on port.
Default = 0.
In Host Mode:
Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one
if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions
to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS
register is also set to one. This bit will automatically change to zero after the resume sequence
is complete. This behavior is different from EHCI where the host controller driver is required to
set this bit to a zero after the resume duration is timed in the driver.
Note that when the Host controller owns the port, the resume sequence follows the defined
sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed
'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the
port has switched to the high-speed idle. Writing a zero has no affect because the port
controller will time the resume operation clear the bit the port control state switches to HS or
FS idle.
This field is zero if Port Power() is zero in host mode.
This bit is not-EHCI compatible.
Intel
Description
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
385
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