High-Speed Serial Interface Transmit Operation - Intel IXP45X Developer's Manual

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HSS Coprocessor—Intel IXP45X and Intel
13.1.2

High-Speed Serial Interface Transmit Operation

For transmission using the High-Speed Serial Interface, each High-Speed Serial
Interface contains five transmit FIFOs, organized exactly as the receive FIFOs. (For
additional details on the FIFO organization, see
Operation" on page
Each transmitted byte is placed into these FIFOs. The data is transmitted using the
High-Speed Serial Interface as a function of a user programmable look-up table (LUT)
and the protocol that is being implemented.
The look-up table will characterize each byte to be transmitted as one of four types:
• Unassigned
• Voice
This characterization will be assigned on a time-slot basis using Intel-supplied APIs.
Assume the same example as before, time slot 0 is be defined as a voice cell, time slot
1 is be defined as an HDLC wrapped packet, time slot 2 is be defined as an undefined
time slot, and time slot 3 is be defined as an 56-K mode cell.
When the HSS transmit interface is ready to process the first byte (time slot 0), the
look-up table will indicate that the byte to be transmitted is a voice cell and needs to be
extracted from the Voice FIFO and placed onto the HSS interface. Likewise, when the
HSS transmit interface is ready to process the second byte (time slot 1), the look-up
table will indicate that the byte to be transmitted is an HDLC cell and needs to be
extracted from one of the HDLC FIFOs and placed onto the HSS interface.
The actual FIFO the byte is extracted from is dependent upon the protocol implemented
and the FIFO arrangement. For more details, see the Intel
Programmer's Guide.
When the HSS transmit interface processes the third byte (time slot 2), the look-up
table will indicate that the byte to be transmitted is an unassigned cell. Using Intel-
supplied APIs, the Intel XScale processor can program the HSS interface to transmit
one of three values in an unassigned time slot:
• All zeros
When the HSS transmit interface processes the fourth byte (time slot 3), the look-up
table will indicate that the byte to be transmitted is a 56-K mode cell and is located in
the Voice FIFO. When the transmit interface detects from the transmit look-up table
that the slot to be transmitted is a 56-K mode byte, only seven of the eight bits in a
time slot will be valid. The most-significant bit or the least-significant bit will be invalid.
Using Intel-supplied APIs, the Intel XScale processor can program the invalid bit
location as well as the value to be placed into the invalid bits location when data is
transmitted. The data inserted into the invalid bit location can be programmed to be
logic 0, logic 1, or tri-state. For more details, see the Intel
Programmer's Guide.
13.2 Feature List
• T1/E1/GCI/MVIP protocols supported in hardware.
• HSS coprocessor split into 'cores', each core houses a set of FIFOs, stream
generator and stream parser. This accommodates re-use of HSS design.
August 2006
Reference Number: 306262-004US
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IXP46X Product Line of Network Processors
724.)
• HDLC
• 56-K mode
• All ones
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Intel IXP45X and Intel
"High-Speed Serial Interface Receive
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IXP400 Software
• High-impedance
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IXP400 Software
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IXP46X Product Line of Network Processors
Developer's Manual
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