Intel IXP45X Developer's Manual page 651

Expansion Bus Controller—Intel
Processors
A clock input, EX_CLK, is required to operate the Expansion interface. The maximum
clock frequency supported by the Expansion bus controller is 80 MHz. The clock input is
provided to allow a wide variety of different peripherals to be connected to the
Expansion interface. The GPIO unit provides a clock output after reset and may be
used. Refer to the GPIO chapter for additional details. If a GPIO clock is used, it must
be externally routed on the board to connect to EX_CLK. This implementation gives the
designer the option to choose between a lower part count and the speed of the
interface operations.
To provide a glue-less interface to a wide variety of devices, the Expansion bus
controller supplies eight chips selects to a 32-bit wide external bus, which can be
configured as Intel, Synchronous Intel, Micron ZBT, Motorola, or HPI-style controls. The
signaling characteristics and timing for each chip select is individually programmable.
After chip reset, chip-select 0 defaults to conservative timing values for controlling an
asynchronous flash device and the data width of the flash is determined by the value of
Expansion Bus Address bits 0 and 7 during the reset sequence. The remaining chip
selects are un-programmed. Refer to
additional details.
For Synchronous Intel StrataFlash Memory, the Expansion bus controller only supports
single word asynchronous page-mode read and synchronous burst-mode read (1-8
words). It does not support page mode read mode or single word latched asynchronous
read mode. When configuring a Synchronous Intel StrataFlash Memory, wait polarity
must be programmed to active low, data hold programmed to one clock, wait delay be
deasserted with valid data and clock edge programmed to rising edge. For 16-bit
Synchronous Intel devices, the burst length must be programmed to 16-word bursts.
For 32-bit Synchronous Intel devices, the burst length must be programmed to 8-word
bursts. The latency count must be programmed to the appropriate code that is defined
in the Synchronous Intel StrataFlash Memory specification.
The Expansion Bus interface signals need to be connected based upon the device type
(Intel, Synchronous Intel, Micron ZBT, Motorola, or HPI-style control signals) and a
sample mapping of the pins are shown in
Table 217. Example Expansion Bus Pin Mappings to Target Devices
Pin
EX_ALE
EX_ADDR[24:0]
EX_BE_N[3:0]
EX_CS_N[7:0]
EX_DATA[31:0]
EX_IOWAIT_N
EX_PARITY[3:0]
EX_RD_N
EX_RDY_N[3:0]
EX_WR_N
Note: The # symbol or an _N suffix in a signal name indicates that the signal is asserted low.
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network
Synchronous
Intel Intel
®
StrataFlash StrataFlash
28F128J3D Embedded
Memory (P30)
OPEN ADV#
A[23:0] A[24:1]
OPEN OPEN
CE# CE#
D[15:0] D[15:0]
OPEN OPEN
OPEN OPEN
OE# OE#
OPEN OPEN
WE# WE#
Intel
"Configuration Register 0" on page 706
Table 217.
Motorola*
MT55L128L36F
MCM6946
OPEN
A[18:0]
OPEN
EN
DQ[7:0]
OPEN
OPEN
G_N
OPEN
W_N
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
for
Micron* ZBT
TI* HPI
TMS320UC5409
1
ADV/LD# OPEN
HCSEL,HCNTL,H
SA
BIL
BW[d:a]# OPEN
CE# hcs
DQ HD[7:0]
OPEN OPEN
DQ OPEN
OE# hr_w_n
OPEN hrdy
R/W# hds1_n
Developer's Manual
651