Intel IXP45X Developer's Manual page 634

Register
Bits Name
RCD: Active to Read or Write Delay in MCLK periods. This value is
computed by using the t
JEDEC/Vendor specification) using the following equation:
Equation 5. RCD = t
22:2
RCD
NOTE: t
0
For example, a device specification yields that t
device speed is 133MHz, so the mclk period is 7.5ns).
t
RCD
Thus, RCD = 3-1 = 2, so a value of 010
19:1
(Reserved)
8
17:1 EDP: Data Path Latency in MCLK periods. A value of 10
EDP
6 programmed for the IXP45X/IXP46X network processors.
15:1
(Reserved)
4
13:1 WDL: Write Data Latency in MCLK periods. A value of 00
WDL
2 programmed for the IXP45X/IXP46X network processors.
11:1
(Reserved)
0
CAS: Indicates the CAS Latency of the memory device (provided in
the JEDEC/Vendor specification).
• 00 = 2 MCLK periods
09:0
CAS
8 • 01 = 2.5 MCLK periods
• 10 = RESERVED
• 11 = RESERVED
07:0
(Reserved)
6
05:0 RESERVED for DDRII. A value of 00
(Reserved)
4 IXP45X/IXP46X network processors.
03 (Reserved)
DDR: Identifies the generation of DDR SDRAM selected by the
MEM_TYPE reset strap. A MEM_TYPE value of 1
the IXP45X/IXP46X network processors.
02 DDR
0 = RESERVED for DDRII/400MHz
1 = DDRI/266MHz
Data Bus Width: Indicates the width of the data bus. See
Data
11.2.2.5, "32-Bit Data Bus Width" on page
used for the IXP45X/IXP46X network processors.
01 Bus
0 = RESERVED for 64 bits
Width
1 = 32 bits
RESERVED for DIMM Type. A value of 0
00 (Reserved)
IXP46X network processors.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
634
® ®
Intel IXP45X and Intel
DDRI SDRAM Control Register 0 - SDCR0 (Sheet 2 of 2)
Description
measured for the device (provided in the
RCD
RCD
must be converted to mclks for this equation.
RCD
= (20ns / 7.5ns) = 2.67, round up to 3 mclks.
IXP46X Product Line of Network Processors—Memory Controller
- 1
is 20ns (and the
RCD
should be programmed.
2
should be
2
must be
2
must be programmed for the
2
must be used for
2
Section
594. A value of 1 must be
2
must be used for the IXP45X/
2
Default Access
000 RW
2
00 RO
2
01 RW
2
00 RO
2
00 RW
2
00 RO
2
00 RW
2
00 RO
2
00 RW
2
0 RO
2
Varies with
external
state of
MEM_TYPE
RO
at reset
Should
default to 1
0 RW
2
0 RO
2
August 2006
Order Number: 306262-004US