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Table 170.
Behavior During Wake-Up Events
Port Status and Signaling Type
Port disabled, resume K-State received
Port suspended, Resume K-State received
Port is enabled, disabled or suspended, and
the port's WKDSCNNT_E bit is a one. A
disconnect is detected.
Port is enabled, disabled or suspended, and
the port's WKDSCNNT_E bit is a zero. A
disconnect is detected.
Port is not connected and the port's
WKCNNT_E bit is a one. A connect is
detected.
Port is not connected and the port's
WKCNNT_E bit is a zero. A connect is
detected.
Port is connected and the port's WKOC_E
bit is a one. An over-current condition
occurs.
Port is connected and the port's WKOC_E
bit is a zero. An over-current condition
occurs.
Notes:
1.
Hardware interrupt issued if Port Change Interrupt Enable bit in the USBINTR register is a one.
2.
PME# asserted if enabled (Note: PME Status must always be set to a one).
3.
PME# not asserted.
9.14.4
Schedule Traversal Rules
The host controller executes transactions for devices using a simple, shared-memory
schedule. The schedule is comprised of a few data structures, organized into two
distinct lists. The data structures are designed to provide the maximum flexibility
required by USB, minimize memory traffic and hardware / software complexity.
System software maintains two schedules for the host controller: a periodic schedule
and an asynchronous schedule. The root of the periodic schedule is the
PERIODICLISTBASE register (see
The PERIODICLISTBASE register is the physical memory base address of the periodic
frame list. The periodic frame list is an array of physical memory pointers. The objects
referenced from the frame list must be valid schedule data structures as defined in
Section 9.6.2, "Host Data Structure" on page
schedule is enabled (see
host controller must execute from the periodic schedule before executing from the
asynchronous schedule. It will only execute from the asynchronous schedule after it
encounters the end of the periodic schedule. The host controller traverses the periodic
schedule by constructing an array offset reference from the PERIODICLISTBASE and
the FRINDEX registers (see
traversing the graph of linked schedule data structures.
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
418
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors—USB 2.0 Host Controller
No Effect
Resume reflected downstream on signaled port. Force Port
Resume status bit in PORTSC register is set to a one. Port
Change Detect bit in USBSTS register set to a one.
Depending in the initial port state, the PORTSC Connect and
Enable status bits are set to zero, and the Connect Change
status bit is set to a one. Port Change Detect bit in the
USBSTS register is set to a one.
Depending on the initial port state, the PORTSC Connect and
Enable status bits are set to zero, and the Connect Change
status bit is set to a one. Port Change Detect bit in the
USBSTS register is set to a one.
PORTSC Connect Status and Connect Status Change bits are
set to a one. Port Change Detect bit in the USBSTS register is
set to a one.
PORTSC Connect Status and Connect Status Change bits are
set to a one. Port Change Detect bit in the USBSTS register is
set to a one.
PORTSC Over-current Active, Over-current Change bits are
set to a one. If Port Enable/Disable bit is a one, it is set to a
zero. Port Change Detect bit in the USBSTS register is set to a
one
PORTSC Over-current Active, Over-current Change bits are
set to a one. If Port Enable/Disable bit is a one, it is set to a
zero. Port Change Detect bit in the USBSTS register is set to a
one.
Section 9.14.6, "Periodic Schedule" on page
Figure 54 on page
Signaled Port Response
Section 9.12.6, "PERIODICLISTBASE" on page
355. In each micro-frame, if the periodic
419). It fetches the element and begins
Device State
Not
D0
D0
N/A
N/A
1,
2
2
1,
2
2
1,
3
3
1,
2
2
1,
3
3
1,
2
2
1,
3
3
379).
425) then the
August 2006
Order Number: 306262-004US
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