Acknowledge On The I; Arbitration; Scl Arbitration - Intel IXP45X Developer's Manual

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receiving each byte from the serial bus. Before receiving the last byte, software must
set the Ack/Nack Control bit to Nack. Nack is then sent after the next byte is received
to indicate the last byte.
In slave mode, the I
independent of the Ack/Nack bit setting in the ICR. As a slave-receiver, an Ack
response is automatically given to a data byte, independent of the Ack/Nack bit setting
in the ICR. The I
byte.
In slave-transmit mode, receiving a Nack from the master indicates the last byte is
transferred. The master then sends either a STOP or repeated START. The ISR's unit
busy bit (2) will remain set until a STOP or repeated START is received.
Figure 195. Acknowledge on the I
Data Output
by Transmitter
(SDA)
Data Output
by Receiver
(SDA)
SCL from
Master
21.5.4

Arbitration

Arbitration on the I
bus. Arbitration is used when two or more masters simultaneously generate a START
condition within the minimum I
Arbitration can continue for a long period. If the address bit and the R/W# are the
same, the arbitration is then handled by the logic level of the data that is being driven.
Due to the wired-AND nature of the I
outputting the same bus states. If the address, the R/W# bit, or the data are different,
the master which outputted the high state (master's data will be different from SDA)
will lose arbitration and shut its data drivers off. When losing arbitration, the I
Interface Unit will shut off the SDA or SCL drivers for the remainder of the byte
transfer, set the Arbitration Loss Detected bit, then return to idle (Slave-Receive)
mode.
21.5.4.1

SCL Arbitration

Each master on the I
With masters generating their own clocks, clocks with different frequencies may be
connected to the SCL line. Since data is valid when the clock is in the high period, a
defined clock synchronization procedure is needed during bit-by-bit arbitration.
Clock synchronization is accomplished by using the wired-AND connection of the I
interfaces to the SCL line. When a master's clock transitions from high to low, this
causes the master to hold down the SCL line for its associated period (see
The low to high transition of the clock may not change when another master has not
completed its period. Therefore, the master with the longest low period holds down the
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
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IXP45X and Intel IXP46X Product Line of Network Processors—I2C Bus Interface Unit
2
C unit automatically acknowledges its own slave address,
2
C unit sends the Ack value after receiving the eighth data bit of the
2
C Bus
1
Start Condition
2
C bus is required due to the multi-master capabilities of the I
2
2
C bus generates its own clock on the SCL line for data transfers.
2-7
C hold time of the START condition.
2
C bus, no data is lost if both (or all) masters are
SDA released
SDA pulled low
by Receiver (ACK)
8 9
Clock Pulse
for Acknowledge
B4260-01
2
2
C Bus
2
Figure 196).
August 2006
Order Number: 306262-004US
C
C