Itd Buffer Page Pointer List (Plus); Itd Buffer Pointer Page 0 (Plus); Itd Buffer Pointer Page 1 (Plus) - Intel IXP45X Developer's Manual

Intel
Table 145. iTD Transaction Status and Control (Sheet 2 of 2)
Bit
15
14:12
11:0
9.13.3.3

iTD Buffer Page Pointer List (Plus)

DWords 9-15 of an isochronous transaction descriptor are nominally page pointers (4K
aligned) to the data buffer for this transfer descriptor. This data structure requires the
associated data buffer to be contiguous (relative to virtual memory), but allows the
physical memory pages to be non-contiguous. Seven page pointers are provided to
support the expression of eight isochronous transfers. The seven pointers allow for 3
(transactions) * 1,024 (maximum packet size) * 8 (transaction records) (24,576 bytes)
to be moved with this data structure, regardless of the alignment offset of the first
page.
Since each pointer is a 4K-aligned page pointer, the least significant 12 bits in several
of the page pointers are used for other purposes.
Table 146.

iTD Buffer Pointer Page 0 (Plus)

Bit
31:12
11:8
7
6:0
Table 147.

iTD Buffer Pointer Page 1 (Plus)

Bit
31:12
11
10:0
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
394
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IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller
Interrupt On Complete (IOC). If this bit is set to one, it specifies that when this transaction
completes, the Host Controller should issue an interrupt at the next interrupt threshold.
Page Select (PG). These bits are set by software to indicate which of the buffer page pointers the
offset field in this slot should be concatenated to produce the starting memory address for this
transaction. The valid range of values for this field is 0 to 6.
Transaction X Offset. This field is a value that is an offset, expressed in bytes, from the
beginning of a buffer. This field is concatenated onto the buffer page pointer indicated in the
adjacent PG field to produce the starting buffer address for this transaction.
Buffer Pointer (Page 0). This is a 4K aligned pointer to physical memory. Corresponds to
memory address bits [31:12].
Endpoint Number (Endpt). This 4-bit field selects the particular endpoint number on the
device serving as the data source or sink.
(Reserved). Bit reserved for future use and should be initialized by software to zero.
Device Address. This field selects the specific device serving as the data source or sink.
Buffer Pointer (Page 1). This is a 4K aligned pointer to physical memory. Corresponds to
memory address bits [31:12].
Direction (I/O).
0 = OUT
1 = IN.
This field encodes whether the high-speed transaction should use an IN or OUT PID.
Maximum Packet Size. This directly corresponds to the maximum packet size of the associated
endpoint (wMaxPacketSize). This field is used for high-bandwidth endpoints where more than
one transaction is issued per transaction description (.e.g. per micro-frame). This field is used
with the Multi field to support high-bandwidth pipes. This field is also used for all IN transfers to
detect packet babble. Software should not set a value larger than 1024 (400h). Any value larger
yields undefined results.
Description
Description
Description
Order Number: 306262-004US
August 2006