Pci Bus Layout Example; 82443Gx Decoupling - Intel 440GX Design Manual

Because of the specifics of an ATX layout, it is recommended that the PIIX4E component is at the
"END" of the PCI bus, as shown in
signals.
Figure 2-28. PCI Bus Layout Example
2.9.5 Decoupling Guidelines: Intel
Decoupling caps should be placed at the corners of the 443GX(BGA Package). A minimum of four
0.1uF and four 0.01 uF are recommended. The system bus, AGP, PCI, and DRAM interface can
"break-out" from the BGA package on all four sides. Additional caps will also help reduce EMI
and cross-talk.
Figure 2-29. 82443GX Decoupling
Note: There are other discrete components for V
routing around the 82443GX.
®
Intel 440GX AGPset Design Guide
Figure
82443GX
0.1uF
0.01uF
0.1uF
0.01uF
Motherboard Layout and Routing Guidelines
2-28. This insures proper "termination" of the PCI Bus
®
440GX AGPset Platform
82443GX
Host Bridge
Controller
492 BGA
, GTL Ref Voltages that must be also considered when
TT
PIIX4E
0.1uF
0.01uF
0.1uF
0.01uF
v006
2-31